Design Manager Jobs

Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world's largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team The Sales Compensation team at Stripe is responsible for the overall compensation strategy, design, and payment administration for the global sales organization. We ensure that our objectives align with the compensation program and that our sales teams are paid accurately and on time. We provide thought leadership for the go-to-market initiatives so that performance and compensation are effectively correlated. The Sales Compensation team partners closely with the revenue-generating and support functions across Stripe to support the success of our sales efforts. What you'll do You're a key contributor to the sales compensation program design, implementation, and performance assessment of the sales organization. You'll have high visibility across multiple channels, owning the performance-to-compensation structure for specific sales teams and serving as the subject matter expert for strategic advice and implementation of any compensation programs (including SPIFFs and MBOs) that further align the sales focus with our OKRs. You're passionate about sales compensation and comfortable working in ambiguous situations to identify optimal solutions for our sales teams to succeed. You have experience working across all levels and functions of an organization (preferably in a high-growth environment) to align our priorities with our sales team's motivation. You bring resilience and the ability to both partner and lead in cross-functional situations. You

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall layout, and optimization of Memory/Logic/Analog layouts Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success Working with Marketing, Probe, Assembly, Test, Process Integration, and Product

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow Hands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of industry standard tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice and Micron-specific simulators Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments and contribute to cross-group communication to work towards standardization and group success About

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow Hands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of industry standard tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice and Micron-specific simulators Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments and contribute to cross-group communication to work towards standardization and group success About M

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations). Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data Support design rule checking (DRC) of both base and mask layers and interface with physical verification team. Define algorithms for generation of mask data from drawn base layer data. Involve projects across multi-disciplinary teams focusing on layout and mask generation issues About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of hig

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has advanced the world’s most innovative memory and semiconductor technologies. As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next‑generation high‑bandwidth memory products. You will evaluate block‑level and full‑chip functionality, solve complex challenges in building, and collaborate with a distributed team to deliver highly reliable, industry‑leading HBM solutions. This role provides the opportunity to contribute to groundbreaking DRAM design, TSV‑based 3D integration, and high‑speed mixed‑signal architectures supporting Machine Learning and AI applications. Responsibilities Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Member of Technical Staff HBM Design Architect, you will be responsible for design and development of high-speed interface between DRAM and Base die in HBM cube! This includes designing the DRAM command and control logic, as well serializing and de-serializing scheme. You will collaborate with a highly creative and motivated development team applying brand-new memory technologies to build groundbreaking HBM products! Responsibilities: Responsible for the high-speed DRAM and Base die interface in HBM cube. Design the DRAM command and control logic, as well as serializing and de-serializing scheme at the interface. Conduct circuit simulations using standard industry simulators such as FINESIM, HSPICE and VERILOG Collaborate with data path design on floor planning and full chip testbench. Analyze timing/area/power in high-speed DRAM or mixed-signal design. Contribute to the development of new HBM product opportunities by assisting with the overall design, layout, and optimization of Memory, Logic, and Analog circuits. Qualifications: Extensive experience with DRAM operation and JEDEC specifications across DDR, LPDDR, GDDR, and HBM product families. Strong technical expertise in analog and mixed-signal circuit design. Hands-on proficiency in DRAM command decoding, bank logic, and RAS/CAS chain design. Demonstrated innovation and problem‑solving capabilities in

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff/Senior Staff Physical Design Floorplan & PDN Lead Experience: 10–14 Years Location: Bangalore/2 days to work Department: RTL-to-GDSII / Physical Implementation Role Overview We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum. As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity. Key Responsibilities Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs. Strategic PDN Design: Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion. EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose ar

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Senior Physical Design Engineer Experience: 4–7 Years Focus: Block-Level RTL-to-GDSII & PPA Optimization Location: Bangalore Hybrid The Role We are looking for a high-energy, technically curious Physical Design Engineer to join our advanced silicon team. This isn't a role for someone who wants to just "push buttons" on a vendor flow. We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape-outs and is hungry to take full ownership of complex partitions. You will be expected to work with a high degree of independence, using your analytical skills to bridge the gap between a standard recipe and a world-class PPA result . You should be comfortable following expert lead direction while maintaining the "question the status-quo" mindset when you see a more efficient path. Key Responsibilities Partition Ownership: Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off. PPA Recipe Development: Don't just run the flow—optimize it. You will perform deep-dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies. Automation-First Mindset: Use Tcl and Python to automate repetitive tasks, build custom analysis scripts, and enhan

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Principal Physical Design Engineer (RTL-to-GDSII) Experience: 14+ Years Technology Focus: Sub-5nm (3nm/2nm) Location: Bangalore Hybrid The Vision We are seeking a Principal Physical Design Engineer who thrives on complexity and rejects the "black box" approach to EDA tools. This role is for a First Principles thinker who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII. Key Responsibilities Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite . PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond. Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations. Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT te

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced physical design engineer with at least 10 years of relevant experience, who thrives in complex, multi-stakeholder projects. Detail-driven, with a strong sense of ownership from synthesis through design closure. Comfortable working at advanced nodes (3nm and below) and multi-GHz designs. A collaborative team player who enjoys mentoring others and influencing methodology. Clear communicator who can balance technical depth with schedule and resource constraints. &nbsp

Archer is an aerospace company based in San Jose, California building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility. We are designing, manufacturing, and operating an all-electric aircraft that can carry four passengers while producing minimal noise. Our sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success. We are dedicated to cultivating an equitable and inclusive environment that embraces our differences, and supports and celebrates all of our team members. What you’ll do: Lead the development of major structural airframe assemblies from preliminary design through certification, and manufacturing ramp up Prioritize task allocation to other team members to achieve the schedule milestones Apply in depth understanding of load paths, design best practices, and hand calcs to design robust structural configurations Apply design for manufacturing concepts to create designs that are cost effective and easy to fabricate at rate. Preferred experience with composite sandwich construction and adhesive paste bonding Develop company standards for composite and metallic part CAD models and drawings Work closely with and mentor other engineers on the design, stress and M&P teams Provide technical guidance on design concepts (risk vs. cost vs. performance) Support manufacturing to validate and verify that designs meet requirements and specifications What you need: 7+ years of experience with lightweight structures (aircraft, spacecraft, other high performance vehicles) Bachelor’s degree in an Engineering field Ability to design and analyze simple components A deep understanding of load paths and laminate design fundamentals Strong CAD skills in NX (preferred), Solidworks, Catia or Creo Familiarity with PDM systems Experience with the manufacturing of composite parts