Dram Design Validation Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned DRAM product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Contribute to effective project-management. Plan and detail your layout, presenting material for global teams to review Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project. Minimum Qualifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. G

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview At the Munich Development Center, we develop high-performance memory solutions for the graphics and AI markets. As part of the DRAM Design Engineering Group (DDEG), we collaborate closely with Micron’s global development and manufacturing teams. Our mission is to push the boundaries of memory technology through innovation, precision, and partnership. Role Overview We are looking for a motivated and curious working student or Master’s thesis candidate to join our DRAM design team. This is an outstanding opportunity to gain hands-on experience in integrated circuit (IC) design while working alongside expert engineers in a collaborative, startup-like environment. You will contribute to real-world projects and receive mentorship to support your academic and professional growth. Responsibilities Support the design and simulation of analog or digital circuit blocks under guidance Assist in developing schematics at the transistor level or RTL Participate in functional verification and layout reviews Contribute to testbench development and simulation setup Document design processes and results for internal use or academic reporting Collaborate with cross-functional teams to understand the full memory design flow Leverage generative AI tools to complete tasks in effective manner Optionally: define and complete a master’s thesis project aligned with team goals Required Qualifications Enrolled in a Bachelor’s or Master’s program in Ele

DRAM Design Engineer (Intern) — Jalisco, Mexico. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of Micron's DRAM Verification organization, you will work within a highly innovative engineering team responsible for verifying advanced memory products that power next-generation computing systems. The team develops and validates sophisticated DRAM technologies that require complex functionality verification, ultra-high-speed operation, advanced low-power capabilities, and power management features. As a DRAM Verification Engineering Intern, you will collaborate with global design and verification teams to ensure the quality and functionality of future DRAM products. You will gain hands-on experience using industry-standard verification tools, simulation environments, debugging methodologies, and advanced verification techniques while contributing to real product development efforts. This role also provides opportunities to employ Artificial Intelligence and AI Assisted tools to improve verification efficiency, analysis, and workflow automation. Responsibilities Perform verification activities including datasheet analysis, verification planning, simulation execution, coverage analysis, debugging, and results review. Support modeling and simulation efforts using industry-standard verification and circuit simulation tools. Collaborate with global design, verification, and multi-functional engineering teams to drive standardization, improve design quality, and support successful product development. Contribute to innovation in future memory technologies by applying adva

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We design the digital foundations that power Micron’s DRAM products used around the world. Our team works at the intersection of circuit design, manufacturing, and systems, collaborating across global sites to solve real silicon problems. We value curiosity, technical depth, Artificial Intelligence and learning from one another as we build memory technology that matters. As a Design Engineer, you will play a critical role in shaping core digital circuits used across all DRAM products. This role offers hands-on ownership of RTL design and optimization while working closely with design, verification, and manufacturing partners. You will contribute directly to product quality, performance, and time-to-market in a collaborative hybrid environment. Responsibilities: Design and optimize RTL for DRAM-related digital circuits and block-level designs Perform STA and drive timing closure across critical paths Collaborate with verification, product engineering, test, and process teams to ensure robust designs Support circuit verification, layout checks, and parasitic extraction analysis Minimum Qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience 6+ years of experience in digital or RTL circuit design Strong experience with RTL design, STA, and timing closure Experience with power delivery network circuit design and optimization Proficiency in UNIX and Cadence design env

New College Grad - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

New College Grad - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Sr. Circuit Design Engineer - DRAM Design — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked, high-performance memories. Apply your knowledge to optimize DRAM designs and architectures for maximum performance, power, and area (PPA). This role is ideal for experienced DRAM designers who will identify, architect, design, and simulate next-generation architectures and memory features in collaboration with experts in stack architecture, memory systems architecture, and SoC microarchitecture. Responsibilities: Identify and develop novel DRAM circuit architectures that anticipate next-generation AI workload requirements, to unlock improvements in bandwidth and energy efficiency. Collaborate with peers to identify the highest-leverage DRAM circuit bottlenecks and define architectural hypotheses. Validate architectural hypotheses through schematic-level circuit design, SPICE simulation, and tradeoff analysis, establishing PPA feasibility. Partner with layout designers to conduct floorplanning studies. Colla

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <l

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Senior Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Unique Opportunities Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: • Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops • Strong judgment to validate AI outputs before use (review assumptions, align with specs/standards, cross-check with simulations, waveforms, assertions, and coverage reports, and document what was accepted/changed) prior to incorporating results into design decisions, verification plans, or debug conclusions • Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Sti