Dram Design Validation Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. HBM Core-Die Architecture & Circuit Design Engineer This role owns next‑generation HBM core‑die architecture and critical DRAM circuit design that directly impact bandwidth, power, area, thermal efficiency, and long‑term reliability. The engineer will drive architecture definition, circuit feasibility, and Architecture Reference Design (ARD) development across advanced 3D‑stacked HBM products. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Key Responsibilities Own HBM core‑die architecture including Bank/Bank‑Group organization, array partitioning, datapath, refresh, and reliability features Drive critical DRAM circuit design and timing closure for row, column, sensing, and datapath paths Develop and optimize architecture solutions for bandwidth, power, area, thermal, and reliability trade‑offs Define and validate refresh, row‑hammer mitigation, data‑retention, and power‑efficient operation schemes Lead architecture feasibility studies using transistor‑level simulation and physical implementa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking an experience high-speed high-speed IO/Clocking Design Engineering at a Principal/Sr Member of Technical Staff (SMTS) level to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop core strategy and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation resu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Intern - DRAM IP Circuits Design Engineer — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s advanced memory design organization, where digital innovation directly shapes the next generation of DRAM products. We work across global teams, combining deep technical expertise with diverse perspectives to solve complex problems and push memory technology forward. We are also deeply engaged with AI tools to develop/optimize the design verification flow for better quality and efficiency This role plays a critical part in defining and delivering competitive digital IP for advanced DRAM. You will influence architecture, design, and verification while collaborating closely with layout, modeling, and CAD partners. It’s a hands-on opportunity to grow your technical depth while making a visible impact on future memory products. Responsibilities: Develop competitive digital IPs for advanced DRAM products Define design and verification requirements from specifications and reference designs Build high-level behavioral and algorithmic models for architecture verification Design IP using RTL or custom methodologies and guide layout and verification teams Collaborate with standards, CAD, modeling, and verification teams to improve design quality Leveraging AI (EX Claude Code or other AI tools) to develop, improve design quality and efficiency Minimum Qualifications: Bachelor’s degree in Electrical Engineering or related field, or equivalent experience 6+ years of experience in digit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power design methodologies, including UPF-based power inten

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Intern Product Yield Enhancement (PYE) Engineer at Micron Technology Inc., you will assist in taking next generation DRAM devices from design to mass production! PYE Engineers are crucial partners between Research and Development, Manufacturing, Product Engineering and Global Quality teams. Our goal is to offer hands-on and substantial engineering projects that allow interns to gain valuable experience with memory systems and the product life cycle while adding impact to Micron’s business. Our intern programs help prepare engineers for future roles and offer an extraordinary experience that supplements your academic experience! The PYE Engineering role is critical to Micron as it serves the company's charter to be the most cost-effective producer of DRAM memory while delivering the quality and reliability that customers expect from the Micron brand. This position is for a 3-month internship. Responsibilities: Your job duties will include detailed DRAM electrical and physical failure analysis. Identify defects introduced by the semiconductor fabrication process. You will data mine using statistical analysis, AI assisted engineering tools, and automation workflows. Find the root cause of failure mechanisms, communicating results with Management, Product, Process and Test Engineering teams. Complete 3-month internship. Minimum Qualifications: Must be pursuing a minimum of a bachelor’s degree in Electrical Engineering, Computer Engineering,

DRAM Product Engineer - LPDDR Design for Test — Taichung - Fab 16, Taiwan. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams. Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis. Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures. Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams. Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams. Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs. Qualifications: Master’s degree i

Design Methodology – Senior / Staff DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we innovate to transform how the world uses information to enrich life. For more than 40 years, we have developed advanced memory and semiconductor technologies that power innovation across industries worldwide. As a DRAM Engineering Group (DEG) Layout Designer at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape out processes and procedures. Our team vision is a continuing desire to develop your skills working in a Team across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity. Responsibilities: Develop and optimize IP layouts for DRAM products while ensuring compliance with design, process, and reliability requirements. Perform physical verification activities including DRC, LVS, EM, quality reviews, and documentation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Design DFT team at Micron, building testability into the heart of advanced memory products. Our work spans circuit innovation, architecture, and methodology, and directly impacts quality, scalability, and manufacturability across Micron’s global portfolio. We collaborate deeply across design, verification, and manufacturing to solve hard problems early and push memory technology forward! As a Design Engineer on the Design DFT team, you play a critical role in ensuring Micron’s memory products are testable, robust, and production-ready. This role blends hands-on circuit design with architectural thinking and forward-looking methodology development. You will influence designs early, partner across disciplines, and help introduce AI-enabled approaches that shape the future of DFT. Responsibilities: Define and implement DFT, testmode, and related design methodology requirements for current and future memory products Design and evaluate new DFT circuit and architectural solutions to improve coverage, scalability, and robustness Influence early design planning by shaping DFT architecture, testability strategies, and reusable design intent Validate DFT solutions through modeling, simulation, and review of circuits, testmodes, and verification results Collaborate across design, verification, product engineering, and manufacturing to meet coverage, cost, and qualit

Staff Design Verification Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.