Dram Systems Architecture Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: Develop system-level solutions, tools, and methodologies to optimize DRAM performance, power efficiency, and cost. Collaborate with multi-functional teams to ideate, evaluate, and implement innovative DRAM and memory system solutions. Analyze system behavior and assess solution effectiveness, making data-driven optimizations and trade-offs. Drive architectural innovation for current and future generations of DRAM technologies. Communicate complex technical concepts clearly and mentor team members through training and technical guidance. Using AI in applicable job functions Minimum Qualifications: Proven experience in memory design and product engineering, memory specifications and operations, or memory system architecture and usage. Minimum of 7 years of experience in the memory or semiconductor industry. Strong understanding of DRAM architectures and system-level interactions. Ability to analyze complex technical problems and drive solutions. Bachelor’s degree in Electrical Engineering, Physics, Computer Engineering, or a related field, or equivalent experience. Preferred Qualifications: Experience with advanced memory technologies such as LPDDR5/6, DDR5/6, GDDR6/7, or HBM3E/4. Strong analytical and problem-solving skills with a passion for innovation. Ability to identify complex technical challenges and develop creative, scalable solutions. Deep under

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We're building memory technologies that power everything from AI to mobile devices. Our team works at the intersection of architecture, system analysis, and product innovation to improve energy efficiency and performance in next-generation DRAM solutions. If you enjoy solving complex technical challenges and influencing product direction through data-driven insights, you'll find exciting opportunities here. As a DRAM Power Engineer you will play a key role in shaping the power efficiency of future AI enabled memory products. You will analyze power behavior, develop models and methodologies, and influence architectural decisions that balance power, performance, and energy efficiency. This role offers broad exposure across engineering disciplines and the opportunity to work closely with teams throughout the product development lifecycle. Responsibilities: Perform AI assisted DRAM power analysis, including IDD characterization, workload-based modeling, and power breakdown analysis Develop and maintain power models, methodologies, and tools to evaluate DRAM architectures and power-performance tradeoffs Translate system and customer power requirements into recommendations that drive architectural and product decisions Define and support DRAM power targets throughout product development Partner with Design, Product Engineering, and System Architecture teams to identify and implement power improvemen

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. DRAM ASIC Architecture Role Overview Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies. This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions. The successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams. Key Responsibilities Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation. Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis coverin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s Compute and Memory Business Unit (CMBU), where we shape how memory powers the world’s most demanding computing platforms. Our team works at the intersection of advanced DRAM technology, system architecture, and emerging AI workloads. We collaborate closely with customers, partners, and internal R&D teams to influence the future of memory-centric system design—and we have a lot of fun doing it! As a Product Architecture Engineer for DRAM, you will play a key role in defining how Micron memory technologies enable AI training and inference platforms. This role blends deep technical exploration with industry engagement and internal collaboration. You will help translate system-level challenges into differentiated DRAM solutions while influencing both customer designs and Micron’s product roadmap. Responsibilities : Explore and evaluate system architectures using modeling, simulation, and prototyping tools Engage customers and partners to identify system bottlenecks and future memory innovations Pathfind AI-focused architectures using LPDDR and DDR DRAM technologies Define and explore DRAM features that increase value in AI and high-performance systems Mentor and coach junior architects and engineers Minimum Qualifications : Bachelor’s degree in Electrical Engineering or equivalent practical experience 10+ years of experience in product engineering or product archit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Department Overview: DRAM Engineering (DRAM Memory) focuses on designing and developing Micron’s industry leading dynamic random access memory products. The team drives process R&D, product design, and technology development for cutting edge DRAM nodes, including DDR5, LPDDR, HBM, and GDDR products that form the foundation of Micron’s global revenue leadership. We work across architecture, engineering, and business teams to evaluate innovative memory solutions and influence product direction. If you’re excited about solving complex challenges in DDR and emerging memory technologies, you’ll find strong impact and collaboration here! We are seeking an experienced Distinguished Member of Technical Staff (DMTS) Design Engineer to join the DRAM System team. This role is at the center of memory innovation. You will analyze current and next-generation memory technologies, identify performance and design gaps, and guide teams on future memory direction. Your work will directly influence architecture, product strategy, and competitive positioning, making it both highly visible and technically rewarding. This position is intended to be part of the Technical Leadership Program at Micron. This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Location: Boise, ID or San Jose, CA Responsibilities:

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development. Define and review module interfaces and system-level architecture. Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate RTL design optimization and design‑space exploration Assist in testbench generation and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom methodology for memory design Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis. Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments. Collaborate closely with architecture, design, verification, and physical design / layout teams. Oversee and manage the layout process including floor-planning, placement, and routing. Perform block-level and full-chip verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools. Contribute to cross-group communication to work towards standardization and group success Provide technical mentorship and participate in design and methodology reviews. Drive innovation into the future memory generations and design methodology within a dynamic w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Leveraging AI for design quality

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Product Architecture Group partners across fabs, test, module, and system teams worldwide to deliver high-performance memory products. We work across geographies and functions to solve complex technical challenges, drive product innovation, and enable industry-leading DRAM solutions. Our team values collaboration, continuous learning, and making a measurable impact through engineering excellence. As a New College Graduate DRAM Yield & Quality Engineer, you will play a key role in monitoring and improving the health of Micron’s server DRAM products. Working with experienced engineers and cross-functional teams around the globe, you will analyze product and manufacturing data, investigate technical issues, and contribute to strategies that improve yield, quality, and performance throughout the product lifecycle. This is a highly visible role with direct impact on customer success and product reliability. Responsibilities Analyze silicon parametric, test, and manufacturing data to identify trends, resolve product issues, and support root cause investigations. Contribute to yield and quality improvement initiatives across new product introduction (NPI), qualification, ramp, and high-volume manufacturing. Collaborate with fab, test, module, quality, and operations teams to drive execution of product health objectives. Develop and maintain automation solutions to improve engineering efficiency, data analysis, and reporting. Apply AI, Agentic AI, and Generative AI tools to en

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities · Lead pre-silicon readiness activities across new DRAM products, including risk assessment, DFMEA preparation, validation planning, and readiness reviews with cross-functional engineering teams. · Partner closely with Design, Verification, Component Validation, Product Engineering, Product Architecture, System Compatibility Group, and Silicon Strategy teams to identify product risks, define validation coverage, and align debug priorities. · Apply strong technical judgment to analyze circuit behavior, silicon data, validation results, failure signatures, and product-level interactions across design, test, and manufacturing flows. · Drive structured investigation and resolution of silicon findings, including root-cause analysis, experiment planning, evidence review, and alignment of mitigation or screen strategies to project milestones. · Influence product readiness decisions by connecting design intent, silicon behavior, validation results, manufacturing constraints, and customer quality expectations. · Mentor engineers, strengthen technical practices, and help capture lessons learned that improve execution, product robustness, and organizational readiness across future DRAM programs. ·Apply AI-enabled ways of working to improve engineering productivity, including use of approved AI tools for technical research, data synthesis, debug plan

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs to ensure functional correctness, performance, power efficiency, and product quality. Develop comprehensive verification plans from architecture and functional specifications in collaboration with architecture and design teams. Create, enhance, and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures. Define and execute coverage-driven verification strategies to achieve functional, assertion, and code coverage goals. Lead debug and root-cause analysis of complex design issues, drive bug resolution, and ensure verification closure. Apply advanced digital and mixed-signal verification methodologies using industry-standard simulation and verification tools. Drive continuous improvements in verification methodologies, automation, regression efficiency, and AI-assisted verification workflows. Collaborate closely with global design, architecture, product engineering, and system engineering teams to ensure successful project execution. Lead verification efforts for major HBM development programs and mentor engineers through technical leadership and knowledge sharing. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. 10+ years of experience in digital and/or mixed-signal design verification with a proven record of deli

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets. Own front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions. Develop, maintain, and optimize design constraints (SDC), including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies to achieve optimal PPA. Collaborate closely with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges, improve design robustness, and ensure successful product execution. Analyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements to meet performance, power, area, and schedule objectives. Chip in to the development and enhancement of design methodologies, automation frameworks, and RTL-to-GDS implementation flows, improving engineering productivity, design quality, and time-to-market. Apply strong expertise in CMOS digital and mixed-signal concepts, Verilog/System Verilog, and industry-standard EDA tools to develop scalable and reliable silicon sol

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years, or MSEE with 5+ years of releva