Engineer Hbm Layout in Jalisco

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Micron Technology is a global leader in memory and storage solutions. As a Validation Engineer for DRAM Compute Products , you will be responsible for preparing, executing, and analyzing validation tests to ensure product functionality and reliability. You will work closely with cross-functional teams to identify and resolve silicon issues, expand validation coverage, and contribute to the development of new testing methodologies. Additionally, we require the use of AI tools and methodologies to improve our efficiency and schedule, resulting in overall savings Responsibilities Prepare validation tests and hardware setups for silicon testing. Execute validation tests and analyze results for accuracy and completeness. Categorize and report silicon issues efficiently. Investigate functionality and margin-related test results. Mitigate software and hardware limitations during validation by working with Design teams to assure quality. Report findings confidently to Design and support root cause analysis. Use Artificial Intelligence (AI) to develop tools, improve processes and shorten overall schedule Minimum Qualifications Bachelor’s degree in Electronics or Electrical Engineering or Master’s degree. 2–5 years of relevant experience. Strong circuit-level understanding, including simulation and debugging. Advanced proficiency in C, C++, and/or Pyth

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned DRAM product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Contribute to effective project-management. Plan and detail your layout, presenting material for global teams to review Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project. Minimum Qualifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build. Key Responsibilities Lead the layout build and physical realization of new memory products. Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets. Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools. Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability. Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing. Produce layout collateral and documentation for cross-team integration. Physical Verification and Tapeout Signoff Run and debug physical verification flows and ensure closure using indust

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. G

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has transformed innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are redefining how the world uses information to enrich life. We are looking for Layout Build engineer at our Micron Technology’s DRAM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Responsibilities: Build and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for timely delivery of block-level layouts with acceptable quality. Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Optimally copresentingith Global engineering teams to assure the success of layout project. Minimum Qualification: Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). <

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