Erc Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role We are hiring an Energy Scheduling & Portfolio Lead to own energy availability across Anthropic's non-cloud data center portfolio: contracted and available energy against planned compute, and the risk to it. This one central scheduling and portfolio role holds the live view of energy availability risk and energy availability need for workload management. You will be our counterpart to the LSEs, QSEs, scheduling coordinators, and suppliers in electricity and gas markets across jurisdictions; forecasting is an instrument of that view. You schedule and manage physical energy delivery — not financial instruments — including how much gas the portfolio needs to schedule, and keep energy supply and the workload plan in step with workload and site planning, energy origination, and data center operations. ESA counterparties operate the behind-the-meter plants; you manage their performance and our exposure. This role will also build processes and structures to ultimately support asset management across our energy portfolio. You are this function's first dedicated owner and will build its models and processes from zero. Responsibilities: Own the live view of energy availability risk and need: contracted, available, and committed energy and capacity at each site against planned load and ramp, by month and by hour where it matters; keep it current as deals sign, sites come online, and plans change, and close gaps and use surpluses with workload and site planning and energy origination. Be the operational counterpart to our LSEs, QSEs, scheduling coordinators, and retail and wholesale suppliers in domestic ISO/RTOs, including ERC

MGR, MTB ERC — Taichung - MTB, Taiwan. Apply via Workday.

Sr. Analyst - Business Data Services 4A — 1415-G ERC: Uppal, Habsiguda, Hyderabad, Telangana. Apply via Workday.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. The Role We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA). Key Responsibilities Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration. Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs. Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below). Cross-Functional Collaboration: Partner tightly with the Physical Design (PD