Hardware Debug And Validation Engineer Jobs

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE The Pure Engineering Team builds the industry’s most innovative, high-performance, and highly available portfolio of products that are designed for the most demanding mission critical applications. Our customers are the most important part of our business and they love our products for its simplicity of management, the constant flow of new and exciting upgrades, and ability to live on the cutting edge of technology while never taking downtime, ever. These new innovations enable our customers to leverage the agility of the public cloud for both traditional IT and cloud-native applications. WHAT YOU'LL DO Responsible for debugging Hardware and System level issues Lead Hardware and Mechanical validation of new drive designs, both internally and with JDM. Includes board level signal/power measurements, mechanical testing, thermal measurements, 4-corner testing, etc… Support interoperability and debug of Pure Storage devices in customer systems Analyze and document test results Perform failure and root cause analysis to support field issues, customer escalation and factory defects Collaborate with cross-functional teams to implement corrective actions and process improvements We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara office in compliance with Everpure's policies, unless you are on PTO, or work travel, or other approved leave. WHAT YOU BRING 7+

About the job Validate the memory and system interfaces that keep advanced AI compute reliable under real product conditions. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across the conditions our customers need. You will build deep understanding of our devices, boards and system behaviour. You will create and execute validation and debug plans for new hardware platforms. Your focus will include LPDDR5-9600, slow-speed interfaces, PCB issues, power behaviour and signal integrity. This is hands-on lab work with real ownership. You will investigate failures, tune memory subsystems and turn complex findings into clear actions across hardware and firmware. The team and culture You will work with Architecture, Silicon Engineering, Hardware Engineering, Firmware, PCB design, power and signal integrity teams. Progress comes through lab evidence, practical judgement and clear debug reports. The team moves quickly because the problems are real and often complex. You will own bring-up activity, drive root cause analysis and keep issues moving across teams. Decisions are made close to the data. You will be expected to speak up, challenge assumptions and help teams choose the right corrective action. What we’re looking for · Strong hands-on hardware debug experience, including board bring-up and subsystem debug · Experience validating and tuning LPDDR memory subsystems, ideally including LPDDR5 · Ability to debug PCB, power, signal integrity and interface issues through to root cause · Knowledge of DDR training, timing optimisation, margin analysis, eye diagrams and stability validation · Confident use of lab instrumentation, including high-bandwidth oscilloscopes, BERT systems and VNA/TDR equipment · Ability to work independently, take responsibility and drive issue resolution across hardware and firmware teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The Team The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The Team The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The

About us At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Reporting to Senior Director of Post Silicon Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. You will lead teams passionate about identifying, reproducing, analyzing, and resolving complex silicon, firmware, and system-level issues during bring-up, characterization, and product readiness. This role combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering fields. The Team The Post-Silicon Debug and Validation team manages bring-up, fault diagnosis, and validation of Graphcore silicon and systems. Our team participates throughout the entire product lifecycle, supporting initial silicon bring-up, subsystem validation, system integration, and production readiness tasks. We coordinate closely with hardware, firmware, software, and systems teams to examine complex failures, develop debug strategies, and advance validation infrastructure. Responsibilities and Duties Lead post-silicon debugging and validation efforts for AI compute silicon and platform technologies Contribute to debug and validation activities across multiple projects and achievements Analyze and address intricate sili

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation CPU and AI silicon. You’ll work at the forefront of hardware innovation, diagnosing complex issues across chips, systems, firmware, and software while collaborating with some of the brightest engineers in the industry. This role offers the opportunity to solve challenging technical problems, build impactful debug solutions, and directly influence the reliability and performance of cutting-edge AI compute platforms. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in hardware debug and post-silicon bring-up for CPU, SoC, or ASIC systems. Strong understanding of processor architecture and microarchitecture (RISC-V, x86, or ARM) with familiarity in debug and trace methodologies (e.g., iJTAG). Hands-on engineer who excels at diagnosing complex hardware, firmware, and software issues through root-cause analysis. Comfortable working in the lab with a passion for building debug tools, automation, and scalable methodologies. Collaborative team player with experience partnering across ASIC, firmware, software, and validation teams. What We Need

About the job Debug the high-speed interfaces that decide whether advanced AI systems perform in the real world. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across real product conditions. You will build deep knowledge of our devices, boards and system behaviour. You will own hands-on validation and debug in the lab, focused on SerDes, PCIe Root Complex and Ethernet. Your work will help resolve complex issues across silicon, hardware, firmware and architecture teams. This role is for someone who enjoys getting close to the hardware. You will tune links, investigate failures and turn difficult lab findings into clear engineering decisions. The team and culture You will work closely with Architecture, Silicon Engineering, Hardware Engineering and Firmware. Progress comes through practical evidence, clear communication and fast problem solving. The team expects ownership without daily oversight. You will drive bring-up, debug issues and help teams reach decisions based on data. You will be trusted to speak up when something is unclear or risky. The best ideas can come from anyone close to the problem. What we’re looking for · Strong hands-on hardware validation experience, including board bring-up and subsystem debug · Experience validating and debugging Ethernet, PCIe Root Complex and SerDes systems · Confident use of lab instrumentation, including oscilloscopes, BERT systems, VNA/TDR equipment and PCIe protocol analysers · Ability to debug signal integrity, protocol-level and interface issues through to root cause · Experience with PCIe bring-up, LTSSM analysis, link training, equalization tuning and interoperability testing · Ability to work independently, take responsibility and drive issue resolution across teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how you

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us, that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale, from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Role Build and evolve our automated hardware-in-the-loop (HIL) validation framework used for ADAS/autonomous driving ECU and system testing. Translate formal validation requirements into repeatable automated test cases covering nominal operation, fault handling, timing, communication integrity, and safety-related behavior. Execute and debug validation on HIL benches using vehicle network interfaces, embedded target access, fault injection, and system emulation. Partner with firmware, systems, and validation teams to define test coverage, investigate failures, and improve release readiness. Support automated regression and release testing, including pre-test firmware deployment, orchestrated test execution, and structured result reporting. Build/Maintain shared framework components as new vehicle platforms, ECU releases, and validation domains are added. About the Work Practical experience with HIL/bench hardware integration (po

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary The Engineering Tool Development Engineer focuses on the design and enablement of engineering tools and solutions for test platforms, with strong emphasis on tester bring‑up, debug, and characterization. This role provides hands‑on technical support in lab environments, integrates lab instrumentation into tester workflows, and ensures reliable data capture for failure analysis and characterization. The position works cross‑functionally with Device Product Engineering (PE), Validation, and Platform teams to standardize tester usage, improve engineering efficiency, and support evolving tester architectures and next‑generation test requirements. Key Responsibilities Tester Tool Design & Enablement Design device‑specific hardware solutions and engineering tester frameworks to support characterization, debug, and validation needs. Develop and refine engineering tools, debug features, and workflows that improve tester usability, observability, and diagnostic capability. Leverage AI‑enabled approaches to accelerate tester program development, bring‑up, and debug, ensuring outputs accurately reflect real tester behavior and silicon response. Engineering Support &am

Job Details: Job Description: The Role and Impact Are you interested in GPU and AI accelerator hardware and want hands-on experience designing and bringing new technology to life? As a GPU & AI Accelerator Hardware Design Undergraduate Intern , you will work alongside experienced engineers developing next-generation GPU and AI accelerator platforms. You will gain practical experience across PCB and board design, power delivery, circuit design, simulation, board bring-up, validation, debugging, and automation. This internship provides an opportunity to apply concepts learned through coursework, labs, research, and technical projects to real-world hardware challenges while collaborating with Intel's cross-functional engineering teams. What You’ll Do Depending on project and team needs, you mayhave the key responsibilities will include but not limited to : Support GPU and AI accelerator board and power design from concept through bring-up and validation. Assist with PCB schematic design, layout, component selection, and Bill of Materials (BOM) development. Learn to troubleshoot challenges involving high-speed board, power, digital, and analog design. Use engineering and simulation tools such as Cadence, Sigrity, SIMetrix, Mathcad, MATLAB, PowerDC, or similar tools. Participate in board bring-up, characterization, validation, and hardware debug. Use laboratory equipment such as oscilloscopes and thermal measurement equipment and support soldering/rework activities. Assist with evaluating power requirements and power-delivery solutions for GPU and AI accelerator designs. Develop or improve test methods and use Python or other scripting languages to automate measurements and data collection. Gain exposure t

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity We are seeking a system validation engineering intern to help drive server blade and rack validation efforts for next-generation AI infrastructure hardware systems. This role focuses on post-silicon system validation across the full lifecycle of server hardware systems, ensuring functional and performance meets product objectives. You will help drive end-to-end blade and rack validation including development, execution, and debug while collaborating across silicon, firmware, systems, and platform teams. The Blade and Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Help drive and execute post-silicon validation goals of AI compute blades and racks including testcase planning, development, and automation Help drive validation testcase execution and system debug against program achievements and report validation progress and risks. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness Triage test failures, collect debug data, and collaborate on root cause analysis. Track validation coverage and continuously improve test processes and infrastructure. What You’ll Bring Working towards a Bachelor's

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. To support our next-generation, high-performance RISC-V CPU architectures and advanced chiplet solutions, Tenstorrent is looking for a hands-on, experienced Post-Silicon Lab Manager. In this role, you will own the post-silicon lab infrastructure and manage operational workflows supporting bring-up, system validation, and customer enablement. You will scale the lab infrastructure to support multiple programs with varied requirements. You will direct post silicon validation engineers on cost building cost effective validation and debug infrastructure. This role is hybrid, based out of Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You hold a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a similar technical field, and you have 8–12+ years in semiconductor hardware, including 3+ years leading a post-silicon validation, characterization, or hardware lab team focused on CPUs. You know high-speed interfaces (PCIe, DDR/GDDR/HBM, SerDes) and fabric links in depth, and you're hands-on with board-level debug tools. You bring a startup mindset. You stay calm and quick when troubleshooting physical hardware unde

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from a diverse group of backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a senior validation lead engineer to lead at-scale rack validation efforts for next-generation AI hyperscale systems. This role focuses on post-silicon system validation across the full lifecycle, ensuring functional, electrical, and thermal performance meets product objectives. You will own end-to-end blade and rack validation including planning, development, execution, and debug while collaborating across firmware, systems, and hardware teams. The Team The Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Responsibilities and Duties Lead post-silicon validation of AI compute blades and racks including test planning, development, and automation. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness. Own execution against program achievements and report validation progress and risks. Triage test failures, collect debug data, and collaborate on root cause analysis. Track

Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug compl