Hardware Systems Architect Jobs

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. What You Might Do Lead RF system architecture and integration for wearable and mobile platforms. Own RF desense investigations and mitigation across the product lifecycle. Define RF specifications, link budgets, validation plans and performance targets. Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios. Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance. Perform CST and ADS simula

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. About the Role We're looking for an experienced Principal Hardware Design Engineer/Manager to lead PCB design and development for next-generation, high-performance cellular base stations. You'll architect the board-level circuitry that complements our custom silicon — spanning digital processing, high-speed SerDes, power management, and RF transmission/reception — to deliver a solution that's both high-reliability and low-cost/power. This opportunity is a high-visibility technical leadership role based in San Diego, CA: you'll own PCB system architecture from concept through qualification, working shoulder-to-shoulder with various domain experts to ensure everything comes together. What You'll Do Own PCB development end-to-end, from concept through production Design and implement RF, analog, digital, and power circuits for high-performance base station products Partner with experts on floor planning and PCB constraints for seamless integration Lead and review schematic capture and PCB layout Optimize PCB stack-up for per

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ is seeking a Senior Power Systems Engineer to drive end to end system architecture, modeling, and optimization for wearable platforms. The candidate will build power models, define system use cases and operating modes, partner with product and engineering teams to meet aggressive power targets, and define manufacturing tests and field telemetry for NPI. The ideal candidate brings strong systems thinking, hands-on experience with low power architectures, and the ability to build models and telemetry to drive tradeoffs from SOC level to board level to maximize user runtime. What You Might Do: Power architecture responsibility for a wearable device covering SoC states, sensor, audio, and memory architecture tradeoffs at board level. Battery, PCM, and charging profile definition and validation Design power experiments, test plans, and measurement & telemetry mechanisms across firmware and hardware to optimize power and performance. Build and maintain system-level power models to model expected power consumption for user profiles. Map power models by subsystem, correlating

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. This role sits at the center of cutting-edge AI hardware development, keeping the servers, PCIe systems, and engineering infrastructure running that power next-generation compute. You’ll be hands-on with rapidly evolving prototype and production systems, installing, maintaining, and troubleshooting hardware in fast-paced R&D and data center environments. Acting as a critical bridge between hardware engineers, software teams, and IT, you’ll help ensure seamless access to the platforms that turn ideas into working silicon and systems. This role is onsite, based out of Toronto, Canada or Austin, Texas. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on hardware professional who enjoys building, maintaining, and troubleshooting complex computing systems. Comfortable working in fast-paced R&D environments where hardware, firmware, and software are constantly evolving. Knowledgeable in computer architecture, operating systems, and hardware diagnostics, with strong problem-solving skills. Collaborative, detail-oriented, and motivated to improve processes through documentation, scripting, and automation. What We Need Inst

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Everpure is seeking a Hardware Engineering Manager to lead a team developing and supporting high-performance storage systems. This role oversees the full hardware lifecycle, from design through production and customer support. The ideal candidate is a strong technical and people leader who can set direction, deliver results, and collaborate across the organization. WHAT YOU'LL DO Lead, mentor, and develop a team of hardware engineers. Set technical direction and execution plans for complex compute, storage, networking, and I/O systems. Own team delivery across architecture, schematic capture, PCB layout, eDVT, qualification, failure analysis, and production release. Harden and evolve hardware validation and qualification strategies, including automated testing, system stress testing, and coverage reviews. Drive root-cause and failure-analysis efforts for internal issues and customer escalations, ensuring corrective actions improve product robustness. Partner with Manufacturing, Operations, Test, Quality, and JDM/OEM partners to transition new hardware subsystems into production. Build scalable engineering processes, automation, documentation standards, and “Quality by Design” practices. Hire and retain top hardware engineering talent while creating a culture of accountability, collaboration, technical excellence, and continuous improvement. Communicate program status, ris

About the Team OpenAI’s Hardware organization develops system and infrastructure solutions optimized for advanced AI workloads. We collaborate across research, software, and external hardware partners to design and deploy next-generation AI systems at scale. Our team works closely with silicon vendors and system partners to evaluate emerging technologies, validate performance characteristics, and ensure that hardware capabilities translate effectively to real-world AI workloads. About the Role We are seeking a 3P Hardware Architecture Expert with deep expertise in GPU and accelerator architectures to engage directly with silicon vendors and guide hardware decisions for AI infrastructure. In this role, you will evaluate architectural tradeoffs across compute, memory, and interconnect systems, translating vendor specifications into real-world workload impact. You will play a critical role in early silicon evaluation, benchmarking, and performance validation, helping ensure that next-generation hardware meets the needs of our workloads. This role is highly hands-on and requires both deep technical understanding and the ability to engage at a high level with partners such as NVIDIA and AMD on architectural direction and design tradeoffs. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Engage deeply with silicon vendors (e.g NVIDIA & AMD) on GPU and accelerator architecture tradeoffs. Analyze and interpret performance, power, and efficiency characteristics of next-generation hardware. Translate vendor specifications into expected real-world performance for AI workloads. Evaluate architectural aspects including: compute throughput and utilization memory systems (HBM, cache hierarchies, bandwidth constraints) data types and precision tradeoffs (FP16, BF16, FP8, etc.) interconnect and scaling behavior. Run benchmarks and profiling to validate hardware performance a

NVIDIA is seeking a Senior System Architect: Heterogeneous EDA Systems to solve a complex challenge in accelerated computing: Failure Attribution at Scale. As EDA or equivalent experience workloads scale across thousands of heterogeneous nodes, a single failure can cause massive resource waste. We need an engineer to develop and build an automated framework. This framework will ingest telemetry from CPU and GPU clusters to identify the root cause of job failures in real-time. It will distinguish between hardware faults, infrastructure instability, and software defects. What you'll be doing: Architect Failure Attribution Frameworks: Build a scalable "flight recorder" for EDA jobs that captures high-fidelity state across the CPU, GPU, and Fabric at the moment of failure. Build automated diagnostics that correlate GPU XID errors, PCIe bus failures, and CUDA memory exceptions. Connect these errors with system-level events such as OOM kills or NUMA-related hangs. Distributed Logging & Tracing: Implement low-overhead tracing mechanisms (using tracing tools or custom agents) that provide access to job execution across multi-node Slurm or Kubernetes clusters. Root Cause Automation: Develop heuristics and models based on machine learning to classify failures as "Hardware Fault," "Software Bug," or "Environment Issue." This reduces the Mean Time to Identify (MTTI) for R&D teams. Resiliency Engineering: Work closely with hardware and infrastructure teams to define "signals of impending failure," enabling proactive job migration or check-pointing before a crash occurs. What we need to see: Distributed Systems Mastery: BS, MS, or PhD in Computer Science or Electrical Engineering (or equivalent experience) with 6+ years in systems programming. Experience building automated

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for an experienced systems software engineer to help define and build the host software stack for our custom next-generation AI systems. You will work close to the hardware on performance-critical software, including Linux kernel drivers, high-throughput I/O paths, and system-scale networking and RDMA. This role spans architecture, implementation, platform bring-up, debugging, and performance optimization. You will work across hardware and software boundaries to make new systems usable end to end, from low-level device interfaces through userspace tooling and production validation. In this role you will: Design, implement, and debug host-side systems software for AI infrastructure, including Linux kernel drivers and supporting userspace components. Build and optimize software paths for high-throughput, low-latency communication, including RDMA and related networking functionality. Develop software around PCIe, DMA, NICs, accelerators, memory movement, and device interaction. Bring up new hardware platforms and diagnose complex issues across kernel, firmware, networking, and hardware boundaries. Build tooling for integration, testing, diagnostics, observability, qualification, and performance characterization. Collaborate with hardware, networking, and platform teams to define interfaces and integrate new capabilities. Work with external vendors where needed to integrate technologies and drive issues to resolution. Contribute across the systems sof

About the job Explore how a next-generation AI architecture behaves from rack scale to data centre scale. As a Senior Systems Engineer, you will investigate a novel AI computing architecture under demanding real-world workloads. You will work on problems where answers aren't readily known, turning curiosity into measurable evidence. You will design experiments, benchmark representative AI workloads and explore how hardware components and software interact at scale. When behaviour is unexpected, you will turn this into new measurements. Your work will help infrastructure engineers, architects and application specialists understand system behaviour, performance, scalability and reliability across the stack. You will also help develop tooling and automation to collect, analyse and visualise system metrics. You do not need to be an AI expert. You will need strong judgement, curiosity and a clear preference for evidence over opinion. You will love this role if you are someone who takes initiative, questions assumptions and enjoys working in areas where the answers are not yet known. The team and culture The System QA team is distributed across multiple locations. We work hard to stay connected and collaborate closely. Our daily team meetings feel more like a virtual coffee break than a formal status update with space to share ideas, ask questions, discuss discoveries and solve problems together. We value trust, autonomy and openness, and we understand that great engineers don't all follow the same career path. What matters is the quality of your work, your curiosity, and your willingness to explore challenging problems. You will have regular 1:1s with your people manager where you will have the opportunity to discuss things that matter to you. You will have dedicated time each week to focus on your CPD. The technical lead will provide direction and help set priorities, but everyone in the team is there to support each other. One of our core principles is tha

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery. In this role you will: Define the architecture and technical roadmap for custom SoCs targeted for edge applications. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments. Collaborate with internal hardware, software, systems, and product teams to align architecture with platform needs. Partner with external silicon vendors, IP providers, and manufacturing partners to execute development plans. Lead hardware/software co-design efforts to maximize performance per watt and end-to-end system efficiency. Guide implementation teams through microarchitecture, RTL development, validation, and bring-up phases. Operate effectively in agile development environments and help teams deliver against aggressive schedules and milestones. You might thrive in this role if: Proven exper

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us—that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale—from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Work Drive the system-level safety architecture and requirements for the Autonomy Hardware and Firmware of the Nuro Driver, ensuring compliance with automotive safety standards such as ISO 26262 and ISO 21448. Decompose vehicle-level Safety Goals into a cohesive Functional Safety Concept (FSC) and refine it into a detailed Technical Safety Concept (TSC), defining system-level safety mechanisms, fault detection and reaction strategies, and safe states. Develop the system-level SOTIF specification for the Autonomy Hardware and Firmware of the Nuro Driver, defining performance targets and acceptance criteria for safety-critical systems like Autonomy Sensors and Compute. Lead, perform, and review system-level safety analyses, including Hazard Analysis and Risk Assessment (HARA), Failure Mode and Effects Analysis (FMEA), and Fault Tree Analysis (FTA), Dependent Failure Analysis (DFA) to identify risks and deriv

*]:pointer-events-auto R6Vx5W_threadScrollVars scroll-mb-[calc(var(--scroll-root-safe-area-inset-bottom,0px)+var(--thread-response-height))] scroll-mt-[calc(var(--header-height)+min(200px,max(70px,20svh)))]" data-turn-id="request-6a61cc6f-a00c-8334-82ca-8a2dd2e477ca-0" data-turn-id-container="request-6a61cc6f-a00c-8334-82ca-8a2dd2e477ca-0" data-testid="conversation-turn-4" data-turn="assistant"> About the job Shape how advanced AI hardware is tested before it reaches customers. You'll lead the technical direction of manufacturing test solutions for Host Processor Modules, Server Blades, and multi-node rack systems. Your work will help ensure every system meets the highest quality standards before deployment. You'll own the architecture of the test executive software and develop manufacturing test content that validates complex hardware at scale. Working across hardware, firmware, and software teams, you'll enable reliable, efficient testing throughout production. This role offers broad technical influence. You'll solve complex engineering challenges, improve manufacturing quality through data, and help shape the future of Graphcore's production test capability. The team and culture You'll join the Product Test and Diagnosis team within Manufacturing Operations. The team defines and delivers test strategies across silicon, boards, server systems, and rack-scale platforms. Day to day, you'll work closely with engineers across hardware, firmware, software, manufacturing, and quality. Decisions are driven by technical evidence, collaboration, and continuous improvement. You'll have the freedom to lead technically, mentor other engineers, and influence how manufacturing test evolves across globally distributed teams. What we're looking for Essential Extensive experience developing and deploying manufacturing test solutions for high-performance servers, accelerators (GPU-class), or comparable large-scale compute hardware. Proven technical leadership as

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Pure Storage is seeking a full-time Principal Hardware Engineer working as part of our Hardware Development Team. In this position, you'll be working to define the technical direction of our next-generation hardware platforms. You’ll work closely with Architects, Engineering, Operations, OEM/JDM Partners and Support & Escalation Teams. You'll be responsible for the future of Pure’s high performance storage systems, acting as the primary subject matter expert for system hardware across executive, product, and client interactions.. WHAT YOU'LL DO Define system-level hardware architecture for FlashBlade, including compute, memory, interconnect, storage, power, and thermal design. Translate product requirements and customer needs into clear technical specifications and design trade-offs. Evaluate and select key components, technologies, and vendors, and lead make-vs-buy decisions. Drive architecture reviews and design reviews, and ensure designs meet performance, reliability, and compliance targets. Partner with firmware and software teams to define hardware/software interfaces and optimize the full stack Track emerging technologies and industry standards, and shape the long-term hardware roadmap. Work with manufacturing and supply chain on DFM/DFT, yield, cost reduction, and component risk. Strong understanding of X86 architecture and proven design track record Solid understanding of Major Bus

About the job Build the hardware that turns new AI processors into working systems. As a Hardware Development Engineer, you will design circuit solutions for Graphcore processor systems and validation platforms. You will turn system requirements into schematics, layout constraints, and testable hardware. Your work will shape production systems and test boards used across development, validation, and customer enablement. You will help prove performance, margin, and reliability before designs move into volume production. Alongside silicon, architecture, software and PCB CAD specialists, you will make design decisions grounded in evidence. You will define validation plans, run lab campaigns, debug prototypes, and interpret results with firmware and architecture teams. This role suits someone who likes owning problems from first schematic to mass production readiness. Few roles connect board design, bring-up, validation, and production so directly. The team and culture Hardware Engineering builds production systems and test hardware around Graphcore processors. The team works close to silicon, architecture, firmware, software, and PCB CAD from the first requirement onwards. Engineers own designs through definition, schematic capture, layout support, bring-up, validation, and production transfer. Work moves quickly because problems are handled close to the lab, not passed between silos. The team makes decisions through evidence: measurements, design reviews, margin data, and open technical challenge. You will speak up, take responsibility, and help the team move with confidence. What we're looking for · Strong digital circuit design and validation skills, including DCDC regulators, power delivery, resets, clocks, and control interfaces. · Experience developing processor-based systems and working with interfaces such as Ethernet, PCIe, DDR, USB, QSPI and JTAG. · Practical lab depth in bring-up, debug, margin testing, and validation using oscilloscopes, logic analysers and

About Graphcore Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data center hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. About the Role We are seeking a Principal Security Architect to design, maintain and secure scalable infrastructure solutions for cryptographic key management. In this strategic role, you will be responsible for evaluating, deploying and manage Hardware Secure Modules from the ground up, ensuring compliance with standards across different regions. You will also enable multiple teams by supporting them for control and automation. You will be expected to drive and implement policies for key and certificate creation, rotation, and revocation. Collaboration with stakeholders to analyze requirements and implement robust access controls is essential while demonstrating operational excellence. RESPONSIBILITIES Design and deploy scalable, secure infrastructure solutions from scratch, aligned with business requirements and security standards. Hardware Secure Module ownership and governance. Develop organizational standards, policies, access models, and workflows to ensure consistent, secure usage of the platform. Conduct risk and compliance assessments to support system security plans and disaster recovery strategies. Collaborate on requirement analysis, user and key story operations, and capacity planning to ensure optimal resource utilization. Advocate for best practices in secret lifecycle management, a