Hbm Advanced Package Process Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of the Heterogeneous Integration Group within Technology and Products, where we build High Bandwidth Memory solutions that power AI and ML platforms. Our team works at the edge of what’s possible, stacking and integrating advanced silicon technologies to deliver industry‑leading bandwidth, density, and power efficiency. We move fast, solve hard problems, and set technical direction others follow! This role sits at the center of next‑generation HBM development. As a senior SI/PI technical authority, you will shape system‑level decisions that directly impact performance, reliability, and scalability across multiple product generations. If you enjoy deep technical ownership, complex problem solving, and influencing architecture from concept to sign‑off, this role offers both challenge and impact. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Lead signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency‑ and time‑domain evaluation Define and drive power delivery architecture, impedance targets, and transient analysis Perform electromagnetic extraction and modeling across PCB, package, and interposer designs Establish SI/PI standards, methodologies, and sign‑off criteria for HBM system designs Provide clear technical direction in ambiguous or incomplete design environments Minimum Qualifications: 7 years of experience in

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As the key talent within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will involve in both intrinsic and extrinsic reliability test program coding for Micron’s latest HBM products. Your responsibility is to develop new reliability test flow (eg: extended wafer level burn in, pWLRx, ELFR etc), both on DRAM and Interface die and a stacked product for extrinsic DPM (Time0 and Field DPM) and intrinsic reliability assessment to meet critical KPI’s Quality, Cost and Cycle Time. You will play pivotal role in ensuring the reliability and robustness of our products through advanced coding practices and comprehensive testing. This position demands a strong grasp of engineering principles, adept problem-solving skills, and a relentless dedication to maintaining high-quality standards. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics. Micron is seeking experienced individuals that find technical challenges engaging and invigorating. Responsibilities: Reliability Test Program Coding: Writing and debugging test programs for HBM device and package qualification

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron Technology’s vision is to change how the world uses information to improve life. Our dedication to people, innovation, tenacity, collaboration, and customer focus helps us fulfill our mission to lead globally in memory and storage solutions. We conduct business with integrity, accountability, and professionalism while supporting our worldwide community. We are looking for Engineers to become part of the Package Development Engineering Team for Advanced Packaging in Singapore. This individual contributor position supports next-generation memory and HBM packaging technologies, concentrating mainly on transitioning new product from development to high-volume manufacturing. The position partners closely with stakeholders such as Development Team & Manufacturing and supplier teams across Micron’s global network. Main Responsibilities Integrate AI-assisted tool and insights into daily work to improve efficiency, quality or effectiveness. Contribute to a culture of continuous improvement by identifying, testing and sharing AI-enablement enhancement within one scope of work. Apply engineering and statistical methods to accelerate learning cycles from Design of Experiments (DOE) through product qualific

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron Technology’s vision is to change how the world uses information to improve life. Our dedication to people, innovation, tenacity, collaboration, and customer focus helps us fulfill our mission to lead globally in memory and storage solutions. We conduct business with integrity, accountability, and professionalism while supporting our worldwide community. We are looking for Engineers to become part of the Package Development Engineering Team for Advanced Packaging in Singapore. This individual contributor position supports next-generation memory and HBM packaging technologies, concentrating mainly on transitioning new product from development to high-volume manufacturing. The position partners closely with stakeholders such as Development Team & Manufacturing and supplier teams across Micron’s global network. Main Responsibilities Integrate AI-assisted tool and insights into daily work to improve efficiency, quality or effectiveness. Contribute to a culture of continuous improvement by identifying, testing and sharing AI-enablement enhancement within one scope of work. Apply engineering and statistical methods to accelerate learning cycles from Design of Experiments (DOE) through product qualific

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Power Delivery Network (PDN) Engineer , you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next-generation HBM products. You will work closely with architecture, design, physical design, packaging, and product engineering teams to ensure robust, efficient, and manufacturable power delivery solutions that meet aggressive performance, power integrity, and reliability targets. This is a hands-on technical role focused on PDN design, EM/IR analysis, and cross-domain optimization across technology, design, and layout. Key Responsibilities Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes. Perform EM/IR analysis and optimization using industry-standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads. Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation. Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks. Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution. Develop and validate power models, including activity-based current profiles and transient analysis for realistic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM and Emerging Memory Quality and Reliability Assurance (DEMQRA) High Bandwidth Memory (HBM) Engineer at Micron Technology, Inc., your primary responsibility will be establishing quality criteria and monitoring quality indices based on FE and BE signals from NPI to high-volume manufacturing (HVM). You will define, lead and drive key action to bring Micron product quality to be the best in class and to prevent quality and reliability related issues from repeat occurrence. Meanwhile, you will involve in developing and supporting qualification stress flows and characterization for HBM and other high performance memory solutions. You will be driving the following: Collaborate with collaborators to define, deploy and monitor outgoing quality and reliability (OQR) metrics based on FE and BE production signals as well as reliability test results Partner with package development engineer and product engineer on latest products and technologies to define quality and reliability fail modes Proactively work to evaluate, characterize, and mitigate Quality and Reliability risks and fail modes for BE new products and HVM Collaborate with MFG Quality Assurance and Quality Engineer teams to improve QR fail mode list for HVM products. Engage with key teams to set and validate OQR specifications and address recognized and potential Quality and Reliability issues Dispo deviation material based on production signals and reliability test results with quick turnaround ti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Validation Product Engineer on High Bandwidth Memory (HBM) technology you will be tasked with developing next-generation HBM products. Product Engineers are a key interface between Design, Manufacturing, Test, and Quality internal departments as well as external customers. We take ownership of HBM products; starting at the Design phase, through initial bring-up, qualification, and into volume production. The seniority level offered will be based on a combination of experience and education. In HBM HIG or equivalent experience (High Bandwidth Memory, Heterogeneous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI. The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design on

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r