Hbm Advanced Package Process Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Signal Integrity (SI) Research & Development team enables the electrical performance of Micron's industry-leading memory and storage products, including DRAM, LPDRAM, NAND, HBM, SSDs, and emerging memory technologies. The team works across silicon, package, PCB, and system-level designs to develop high-speed signaling and power delivery solutions that support next-generation computing, AI, networking, automotive, mobile, and data center applications. As a Signal Integrity Engineer, you will support the design, analysis, and validation of high-speed memory interfaces and power distribution networks across Micron's product portfolio. Working alongside experienced engineers, you will use modeling, simulation, measurements, and AI-enabled workflows to evaluate signal and power integrity performance, support product development, and contribute to future technology and industry standards initiatives. Responsibilities Support signal integrity and power integrity analysis for high-speed memory interfaces and power distribution networks through modeling, simulation, measurement, and correlation activities. Collaborate with silicon, package, product, validation, and system engineering teams to ensure product electrical performance across all stages of development. Develop and evaluate die, package, PCB, and system-level models to identify performance risks and optimization opportunities. Apply AI-enabled tools and agentic workflows to improve engineering efficiency, automate analysis, improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive cross-functional collaboration across Design, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor junior engineers and provide technical leadership to project teams. Define and improve design methodologies utilizing AI-enabled tools, automation, and best practices. Support silicon bring-up, debug, characterization, and yield improvement activities. Communicate project status, risks, and mitigation plans to management and stakeholders. Required Qualifications BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. 8+

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Build, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor engineers with less experience and provide technical leadership to project teams. Define and improve compose methodologies applying AI-enabled tools, automation, and protocols. Support silicon bring-up, debug, characterization, and yield improvement activities. Communicate project status, risks, and mitigation plans to management and collaborators. Required Qualifications BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Location: Richardson, TX We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Design, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities · Lead the design and execution of sophisticated memory subsystems and top-level integration activities. · Own design planning, technical decision-making, risk assessment, and schedule execution. · Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. · Review design specifications, microarchitecture documents, and implementation plans. · Drive memory array design, including address decoders and data path, internal power supplies, and custom circuit design activities depending on project needs. · Lead design reviews and drive issue resolution across organizations. · Guide engineers who are developing their skills and provide technical leadership to project teams. · Define and improve building methodologies by applying AI-enabled tools, automation, and guidelines. · Support silicon bring-up, debug, characterization, and yield improvement activities. · Communicate project status, risks, and mitigat

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Building, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor early-career engineers and provide technical leadership to project teams. Define and improve develop methodologies applying AI-enabled tools, automation, and standard processes. Support silicon bring-up, debug, characterization, and yield improvement activities. Communicate project status, risks, and mitigation plans to management and collaborators. Required Qualifications BS/MS/PhD in Electrical Engineering, Computer Engineering,

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Staff Engineer in Micron’s High Bandwidth Memory (HBM) Component Validation team, you will contribute as Subject Matter Expert (SME) and contribute to define new standards on validation development for advanced HBM products and ensure stable, scalable validation testing infrastructure with zero code-related escapes across various test flows and high speed memory validation. You own optimizing test flows, and lead technical problem solving for next generation HBM products. You’ll drive validation development deliverables and mentor junior engineers. Why Join Us You’ll gain hands-on experience with cutting-edge HBM technologies and validation platforms, working alongside global experts. This role offers opportunities to learn advanced validation techniques, drive and deliver product readiness, technology solutions and innovations, and grow into technical leadership roles. Responsibilities: Test program development SME: Drive and develop and maintain test programs for HBM component validation Deliver timely test program releases aligned with validation milestones and drive code quality, reviews, and release best-practices Drive test time optimization and parallelism improvements Drive tes

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Staff Engineer in Micron’s High Bandwidth Memory (HBM) Component Validation team, you will contribute as Subject Matter Expert (SME) and contribute to define new standards on validation development for advanced HBM products and ensure stable, scalable validation testing infrastructure with zero code-related escapes across MBIST, Native test modes and high speed memory validation. You own optimizing test flows, and lead technical problem solving for next generation HBM products. You’ll drive validation development deliverables and mentor junior engineers. Why Join Us You’ll gain hands-on experience with cutting-edge HBM technologies and validation platforms, working alongside global experts. This role offers opportunities to learn advanced validation techniques, drive and deliver product readiness, technology solutions and innovations, and grow into technical leadership roles. Responsibilities Test program development SME: Drive and develop and maintain test programs for HBM component validation Deliver timely test program releases aligned with validation milestones and drive code quality, reviews, and release best-practices Drive test time optimization and parallelism improvements Drive test stab