Hbm Process Equipment Engineer Jobs

Staff Design Engineer/Architect, HBM — Richardson, TX. Apply via Workday.

Staff Design Engineer, HBM — Richardson, TX. Apply via Workday.

Principal Analog Design Engineer, HBM — Richardson, TX. Apply via Workday.

Staff Engineer, HBM Verification Architecture — Richardson, TX. Apply via Workday.

Principal Memory Design Engineer, HBM — Richardson, TX. Apply via Workday.

Engineer, HIG HBM, Product Engineering (Media Health Reliability) — Fab 10A, Singapore. Apply via Workday.

Sr Design Verification Engineer, HBM Verification Architecture — Richardson, TX. Apply via Workday.

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing) — Fab 10A, Singapore. Apply via Workday.

Sr Design Engineer, HBM — Richardson, TX. Apply via Workday.

ENGINEER, High Bandwidth Memory (HBM) & New Product Introduction (NPI) — MSB, Singapore. Apply via Workday.

Sr Design Engineer, HBM — Richardson, TX. Apply via Workday.

Memory Design Engineer, HBM — Richardson, TX. Apply via Workday.

ENGINEER, PDE HBM NPI — Taichung - Fab 16, Taiwan. Apply via Workday.

Principal DFT Engineer, HBM — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<