Ip Counsel Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join Tenstorrent’s AI IP software team and help customers bring AI workloads to products built on Tenstorrent technology. In addition to building our own hardware platforms, Tenstorrent offers AI acceleration IP that customers can integrate into their own SoCs. You’ll work directly with those customers to help bring models into Tenstorrent workflows, answer technical questions, and solve integration challenges. This is a broad, hands-on software role spanning models, compiler and runtime workflows, and AI IP. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A strong software engineer who enjoys working across a broad technical stack and learning new tools and workflows quickly. You have a working understanding of machine learning fundamentals and common model architectures, especially computer vision models and large language models. You don’t need to be an ML researcher or an expert in every architecture. A practical problem-solver who can turn customer questions and ambiguous requirements into clear investigations and workable solutions. A collaborative communicator who enjoys workin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Complete ownership of verification and end to end analysis of complex block level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5, DDR6 and LPDDR6 that are capable of operating at high speeds of up to 11,4000MT/s. Staff-Level Expectations: At the Staff level, engineers are expected to: Lead verification efforts for strategic IPs and complex subsystems. Influence verification methodology across projects. Mentor junior engineers and drive verification quality, productivity, and innovation. Provide technical leadership across geographically distributed teams. Ability to lead team, guide and set the direction for the verification effort for any project that the team undertakes. Define roadmap and future scope of verification methodologies. Roles and Responsibilities: Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM) Run directed and constrained-random tests and regressions; analyze results and triage failures. Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. You will work at the hardware/software boundary to define how those hardware blocks are initialized, coordinated, and used by the runtime. You will determine how workloads are dispatched, scheduled, synchronized, and executed across the accelerator, while solving complex performance problems through implementation, bring-up, and debugging. This role is hybrid and based in Toronto, ON or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert C or C++ engineer with a track record of designing and delivering complex, performance-critical systems. Experienced working close to hardware in low-level, embedded, bare-metal, or accelerator environments and translating hardware specifications into reliable software behavior. Strong in runtime fundamentals, including command execution, scheduling, synchronization, memory movement, resource management, and parallelism. Skilled at debugging and optimizing systems end-to-end, especially at the hardware/software boundary. A technical leader who collaborates effectively across hardware, firmware, compiler, and systems teams and mentors other engineers. What We Need Define the runtime architect

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon IP designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Good understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing experience is encouraged. Hands on experience in building SPICE testbenches at Block, Fullchip Level. Hands-on experience in building the COSIM/ Mixed signal verification environment is encouraged. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills us

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In-depth understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview. Experience in debugging complex Analog/Digital/Mixed-Signal circuits is mandatory. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing. Hands on experience in building SPICE testbenches at Block, Fullchip Level. Hand on experience in building the COSIM/ Mixed signal verification environment. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using perl, python is a plus. Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team. Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks. Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions. Bachelor’s with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the w

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP. You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies. You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify. Work with HW architects and designers to make the right implementation choices. You will be working with architects, designers, and other members of yo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The DRAM IP Development (IPDEV) team develops critical digital IP solutions that enable next-generation AI, mobile, client, data center, and graphics memory products. Our team is responsible for delivering high-quality DRAM IPs that drive innovation, product performance, and development efficiency across Micron's memory portfolio. As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside experienced engineers to develop and validate digital IP circuits used in future DRAM products. This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will contribute to impactful engineering projects while gaining exposure to industry-standard EDA tools, multi-functional collaboration, and AI-enabled engineering workflows. Responsibilities Support the design, development, and verification of digital IP circuits for next-generation DRAM products using RTL-to-GDS methodologies. Perform circuit analysis across process, voltage, and temperature (PVT) corners to evaluate performance, quality, and reliability. Develop automation scripts and leverage Agentic AI, AI-Assisted tools, or Code Assist solutions to improve engineering productivity and design quality. Collaborate with multi-functional engineering teams on design implementation, verification,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As the Assembly and Test (AT) IP Security Engineer, you will be part of the AT BISO (Business Information Security Officer) Organization. You will partner with Micron’s Enterprise Infrastructure and Security (EIS) and your business area (Assembly and Test) to implement security controls, reduce risk, and maintain business continuity. You will work within Assembly and Test organizations (and sites) to identify risks, help classify data and establish processes which are aligned to Micron’s security disciplines. You will serve as an ambassador for Assembly and Test Organization to protect Micron’s most sensitive data (Intellectual Property). You will institutionalize a security-first culture across AT operations and ensure compliance with micron’s security standards, whilst ensuring AT Business continuity Key Responsibilities Act as a Liaison with EIS team and AT business are to support roadmaps, strategies, and requirements to improve Micron’s security policies. Bridge security goals and commitments with articulated business needs driving towards a common set of goals and objectives Participate in defining clear goals and strategic initiatives to improve our security posture in line with Micron’s 7 Security Disciplines. Secure Data Handling: Help secure micron’s most Sensitive Data (Sensitive Data Protection Program), through Data Classification and Inventorization. Help define and implement Entitlement Policy Management System (EPMS) fo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As the Assembly and Test (AT) IP Security Engineer, you will be part of the AT BISO (Business Information Security Officer) Organization. You will partner with Micron’s Enterprise Infrastructure and Security (EIS) and your business area (Assembly and Test) to implement security controls, reduce risk, and maintain business continuity. You will work within Assembly and Test organizations (and sites) to identify risks, help classify data and establish processes which are aligned to Micron’s security disciplines. You will serve as an ambassador for Assembly and Test Organization to protect Micron’s most sensitive data (Intellectual Property). You will institutionalize a security-first culture across AT operations and ensure compliance with micron’s security standards, whilst ensuring AT Business continuity Key Responsibilities Act as a Liaison with EIS team and AT business are to support roadmaps, strategies, and requirements to improve Micron’s security policies. Bridge security goals and commitments with articulated business needs driving towards a common set of goals and objectives Participate in defining clear goals and strategic initiatives to improve our security posture in line with Micron’s 7 Security Disciplines. Secure Data Handling: Help secure micron’s most Sensitive Data (Sensitive Data Protection Program), through Data Classification and Inventorization. Help define and implement Entitlement Policy Management

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes. Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets. Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout. Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage sc

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (T

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Software Driver Developer to create reference drivers for our AI-IP in a reference system. You will also support our AI-IP customer optimizing our reference driver into our customer specific systems. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deep systems engineer with 7+ years of experience in device drivers or low-level systems programming. Strong proficiency in C and C++ with a solid understanding of hardware-software interfaces. Hands-on experience developing Linux kernel drivers, including kernel architecture, debugging, and kernel-space/user-space interactions. Experience developing drivers for high-speed I/O or interconnect technologies such as PCIe; PCIe driver development is strongly preferred. Familiar with user-mode and kernel-mode driver models and understands that Linux kernel driver development differs meaningfully from bare-metal or RTOS-based driver development. What We Need Design and evolve the driver layer that provides high-performance APIs for Tenstorrent devices. Develop and maintain user-mode and kernel-mode drivers for Te

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In-depth understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview. Experience in debugging complex Analog/Digital/Mixed-Signal circuits is mandatory. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing. Hands on experience in building SPICE testbenches at Block, Fullchip Level. Hand on experience in building the COSIM/ Mixed signal verification environment. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using perl, python is a plus. Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team. Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks. Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions. Bachelor’s with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM) Run directed and constrained-random tests and regressions; analyze results and triage failures. Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout Provide verification support to design projects by simulating, analyzing, and debugging block level RTL. Develop Test cases/Stimulus to increase the functional coverage for all DRAM architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Debug RTL / testbench / environment issues and partner with design engineers to identify root cause, propose fixes, and prevent recurrence. Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure. Good understanding of digital circuits and experience in RTL Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium. Hands on experience in buildin