Macro Quant Researcher Jobs

At NVIDIA, we push the boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC Verification Engineer - GPU means working on modern technology powering consumer graphics and AI applications. This position is ideal for those passionate about technology and eager to impact computing’s future. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. You will be responsible for verifying the ASIC build, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent. Understand the design and implementation of your unit/cluster/chip, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Collaborate with architects, designers, and pre- and post-silicon verification teams to accomplish your task. What we need to see: Bachelor's Degree in EE, CS, or CE or equivalent experience. 5+ years of relevant experience. Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, Indago, GDB). Expertise in System Verilog or similar HVL. Strong debugging and analytical skills. Perl and C/C++ programming language experience desirable. Strong communication skills and the ability & desire to work as a great teammate are huge pluses. Experience in crafting test bench environments for unit and system level verification. #LI-Hybrid Your base salary will be det

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks What we need to see: Bachelors Degree in EE, CS or CE or equivalent experience 2+ years of relevant experience Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB) Experience crafting test bench environments for unit and system level verification Strong background in System Verilog or similar HVL Expertise with C/C++ programmin

Location: Mumbai, Maharashtra/ Chennai Ambattur Key Responsibilities: Gather, analyze, and document business requirements for Temenos Infinity / Digital Banking implementations, translating them into functional specifications and user stories. Facilitate requirement elicitation workshops with business stakeholders to define digital origination, onboarding, and servicing journeys. Document current and future-state business processes, workflows, and use cases for CSR journeys and Digital Banking Servicing Micro Apps. Collaborate with technical consultants to configure and validate Visualizer-based journeys aligned to business requirements. Define and review BPMN and DMN process flows and task workflows supporting business operations. Conduct gap analysis between standard Temenos Infinity functionality and client-specific requirements, proposing configuration or extensibility options. Prepare Business Requirement Documents (BRDs), Functional Specification Documents (FSDs), and requirement traceability matrices. Translate business requirements into technical inputs for Fabric Experience APIs and Temenos Digital Microservices configurations. Plan and support User Acceptance Testing (UAT), including test case design, execution support, and defect triage with business stakeholders. Liaise between business stakeholders, technical teams, and project management to ensure requirements are correctly understood and delivered. Assist with change impact assessments, training material preparation, and end-user training for Temenos Digital solutions. Contribute to solution design discussions, ensuring alignment with business goals, scalability, and regulatory requirements. Track, manage, and obtain sign-off on requirement changes throughout the project lifecycle. Support pre-sales and solution consulting activities, including RFP responses and solution demonstrations, as required. Share domain and functional knowledge, providing guidance and training to internal teams o

NVIDIA is seeking a world-class computer architect to contribute to the development of future high-performance computing systems, with a focus on enhancing the power-constrained performance of the hardware. Ideal candidates will have a strong track record of understanding and analyzing memory systems architecture to improve performance per watt (perf/W) and performance per millimeter (perf/mm). A broad perspective across the field of computer architecture and depth in the area of power, performance, and area (PPA) analysis is highly desirable. NVIDIA has pioneered programmable GPUs and the CUDA language and is a world leader in high-performance computing technology, with aggressive plans for future processors. This position offers the opportunity to have a real impact in a fast-moving, technology-focused company. What you will be doing: Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro-architecture features to improve the state-of-the-art in GPU memory systems, optimizing along the axes of perf/W, perf/mm, and perf/$. Develop and enhance architecture prototype models for power and noise analysis. Participate in performance and power simulation of features to analyze, define, and improve energy per byte. Analyze benchmarks, application workloads, and performance/power simulation and emulation results to identify areas for architecture optimizations. Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. Collaborate with outside partners on system infrastructure. What we want to see: 10+ yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. Bachelor

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Responsibilities Perform electrical and physical failure analysis for device anomalies, customer returns, and qualification failures. Apply advanced FA tools including FIB/EDX, SEM, Ion Millers, CSAM, 2D/3D X-ray, Emmi systems, micro-prober and bench tester. Analyze test data failures using Bash/Python scripting in a Unix environment. Analyze electrical signatures and physical defects to resolve failure mechanisms. Collaborate with process owners and Product teams to drive improvement actions. Develop and implement new FA techniques to reduce turnaround time and enhance accuracy. Drive continuous improvement initiatives and embrace standards for FA workflows. Ensure strict consistency to lab safety protocols and chemical handling guidelines. Maintain +6S standards in the FA lab. Prepare detailed FA reports and maintain accurate records for traceability. Present findings to requestors, MRB and multi-functional teams. Provide guidance to FA technicians and lead workload distribution. Work closely with vendors for tool upgrades and capability improvements. Utilize AI-enabled tools and digital

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root caus

At Lyft, our purpose is to serve and connect. We aim to achieve this by cultivating a work environment where all team members belong and have the opportunity to thrive. Lyft’s Bikes & Scooters team is developing the future of micro-mobility and we are looking for a solid, experienced Software Engineer to join our Stations Software Platform team to work on helping us transition our customers to our latest generation platform and to make the platform evolve in a solution that can be brought to multiple different markets and business models. Technical interviews and interactions with the other offices in the company will be in English; however, the working environment in Montreal is bilingual. Responsibilities: Help define the roadmap and architecture based on technology and business needs Write well-crafted, well-tested, readable, maintainable code Have a good grasp and ability to explain the various tradeoffs made in decisions Participate in code reviews to ensure code quality and distribute knowledge Lead projects from idea to positive execution Incorporate considerations for business context and failure modes in your work Proactively participate in resolving ongoing incidents Unblock, support, effectively communicate and obtain buy-in across teams to achieve results Share your knowledge by giving brown bags, tech talks, and evangelizing appropriate tech and engineering best practices Experience: BSc/MSc in Computer Engineering, Computer Science, related field or relevant work experience 5+ years of software engineering industry experience Experience with object-oriented programming Experience in distributed systems Experience with Java and/or Python, familiarity with Scala is a plus Experience working with databases, relational or NoSQL Experience writing clear, scalable and clear design documentation Experience designing, building and improving a set of team owned components Must have a track record of professional excellence Benefits: Extend

High Performance Workstation Business Development Manager- AMD Description - Sales and Technical Consultant, High-Performance Workstation Segment We are seeking a customer-facing AI and Acquisition subject matter expert role on the HPI Advanced Compute Solutions (ACS) sales team and will focus on growing HP’s Z high-performance workstation Total Addressable Market (TAM) within the AI PC market. This individual will be responsible for working with customers and partners in support of attracting new customers and growth in HP’s high performance compute solutions . The role analyzes market competition, gathers customer feedback, and shares insights with internal teams for improvement. The ideal candidate will possess a breadth of abilities and skills, including client hardware knowledge, AI and machine learning applications and solutions, strong marketing and presentation skills, solid understanding of customers’ business and decision makers, and strong team leadership to drive growth with an emphasis on Advanced Micro Devices (AMD) platforms with customers and partners. Most importantly, the role offers the opportunity to be a business leader in support of the sales teams nationally - contributing to the strategy, setting direction, and achieving success in AMD and HP. The role requires someone to be self-driven, capable of operating autonomously through ambiguity, and constantly striving for excellence. THE PERSON: We seek an individual with exceptional technical & business knowledge and familiarity with AI trends in the PC market. This individual should be comfortable working: Dynamic environment and have experience with PC client and AI hardware, software and systems. Work independently within a core team is important, and you will rely upon your excellent communication and relat

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Work in a combined design and verification team which develops some of the switch silicon core units. Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: B.Sc. in Electrical Engineering or Computer Engineering. 4&#43; years of experience in RTL design or RTL verification. Previous experience in networking - an advantage. A team player with good communication and interpersonal skills. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field. #LI-Hybrid <

About the Team You will join the Fulfilment and Experience (F&E) team at Meesho. F&E is the operational and technological backbone powering India’s most cost-efficient, reliable, and scalable e-commerce network, serving 100M+ monthly active users. From disintermediating traditional logistics through Valmo (Meesho’s unbundled micro-entrepreneur supply platform) to driving zero-commission seller enablement and real-time speed platforms, F&E operates at the intersection of deep systems thinking, network engineering, and structural innovation. We solve industry-defining supply chain problems at a scale that few companies globally can match. About the Role This role offers a direct mandate to reshape a function that touches every single Meesho order, with full autonomy over team structure, roadmap, and how you solve the problem. It also gives you a seat at the table with senior leadership on one of Meesho's most visible 2-year bets, while allowing you to work at the intersection of scale (India's largest value e-commerce platform) and zero-to-one building. What You Will Do Order-to-delivery experience — speed, reliability, and predictability of the fulfillment promise Post-order experience — returns, refunds, and how fast/painlessly they resolve Customer support — treating support volume as a signal to fix root causes, not just a queue to clear The fast delivery network bet — reimagining what "fast" means for value e-commerce, and what infrastructure/network changes get us there A team of 10–15 — you'll build, coach, and scale a pod of builders (not just managers) What You Will Need B.Tech/MBA from a premium institute preferred 5–8 years overall experience; 2+ years in management consulting, strategy & ops, or a startup/tech environment (e-commerce or logistics preferre

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems. Experienced in CPU

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a member of the ASIC Design team, you will work on design tasks for Micron's next generation of solid-state drive controllers. You will be involved in various phases of the ASIC design process, from concept to production silicon. This includes writing micro-architecture specifications, implementing RTL design, collaborating with the verification team to fully validate the design, delivering a gate netlist to the back-end implementation team to meet timing and physical constraints, and developing scripts to improve the design process. The ideal candidate is highly motivated, detail-oriented, and possesses excellent documentation and communication skills. Strong collaboration skills and a commitment to completing tasks with high quality are essential. This role additionally expects familiarity with AI assisted engineering tools to improve productivity, accelerate debugging, and enhance documentation quality, while ensuring responsible and secure usage. Responsibilities: Design, implement, and debug complex logic designs. Integrate your IP into larger and more complex IPs. Support front-end integration activities such as Lint, CDC, Synthesis, and ECO. Implement design automation using Python or other programming languages. Collaborate with SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams. Work closely with software and systems teams to ensure high-quality system integration.<

What We’re Looking For: We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort. Ideal Candidates: Ideal candidates will have: Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them Experience both with in-house and outsourced physical design flows Nice to Have: Experience with physical design process for multi-die/multi-chiplet/MCM designs Experience with physical design process for reticle-max or near reticle max designs Experience with very high power density chips Experience with the physical design process for AI chips Experience with the physical design process of analog and mixed signal blocks and macros

A World-Changing Company Palantir builds the world’s leading software for data-driven decisions and operations. By bringing the right data to the people who need it, our platforms empower our partners to develop lifesaving drugs, forecast supply chain disruptions, locate missing children, and more. The Role The Palantir Design Team is responsible for the human experience of using our software. Our team is growing rapidly, but we're committed to creating a tight-knit team environment that fosters trust, integrity, empathy, and growth. We work together in realizing a shared product vision, and regularly give feedback and critique to each other. Designing at Palantir is a varied experience. On a given day, you might be: leading a design sprint for your product team; designing a micro-interaction to make a complex analytical task feel simple; and/or advocating for UX consistency by creating flexible, reusable UI components. Core Responsibilities As a Product Design intern, your responsibilities look similar to a full-time designer, with the resources, stability, and mentorship of an established tech company. You’ll work on product teams with minimal supervision and own end-to-end execution of real product features. You will work with fellow Designers, Product Managers, Developers, and Forward Deployed Engineers to refine and evolve the quality of Palantir products. Interaction and visual design . You'll be involved at every stage of design work. You'll help define early product concepts, flesh out the high-level workflow and micro-interactions of a feature, and execute on a crisp and effective visual design. You should have experience designing and prototyping using tools such as Figma. User research . We frequently do informal user research, and value people who can be flexible with research processes and methodologies to achieve the right outcome. You'll often visit customer offices to interview and learn

What We’re Looking For: We’re looking for a PHY/SERDES Lead to own and lead the development of our semi-custom optical PHY layer. Ideal Background: Multiple successful tapeouts of SERDES or PHY macros (not necessarily only chiplet interfaces, SERDES also counts here) Deep understanding of tradeoffs between XSR/VSR/LR class SERDES and different operating regimes and challenges Understanding and ownership of end to end link definition and architecture Experience with bringup of PHYs Understanding of the integration of PHYs into the system level Strongly Preferred: Deep knowledge of and hands-on with chiplet interfaces like UCIe or BoW Deep knowledge and hands-on execution of optical interconnect PHY layers Knowledge of re-driven and re-timed PHY interfaces Experience with customization of PHYs