Methodology Jobs

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5+ years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: Join our ambitious and innovative team dedicated to optimizing world-class engineering solutions at Micron. Our department thrives on collaboration, precision, and a drive to push boundaries in information technology. Position Overview: As a MGR, IE AMHS SYSTEM, you will play a crucial role in the flawless execution of our business strategies and goals. This position offers an outstanding opportunity to lead and innovate in the field of automated material handling systems within a dynamic and encouraging environment! Responsibilities: Coordinate the installation, relocation, removal, and upgrades of AMHS and Sorter/BWS/N2 Purge tools. Collaborate with vendors to resolve problems, defect issues, and improve tool availability. Participate in CST meetings to benchmark domain knowledge and improve area tool management. Optimize tool performance in line with the company’s business plan, strategies, and goals. Drive area tools improvement projects and provide related project support. Forecast, plan, and track the area budget while implementing cost reduction initiatives. Using Artifical Intelligence methodology to find out the opportunity of improvement. Using AI Applying AI Leveraging AI Minimum Qualifications: Possession of a Bachelor's degree in Engineering or a related area, or comparable practical experience. Proven experience in AMHS systems and tool management. Strong

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: We are searching for an HBM IO Design Architecture Engineer to build and own the end-to-end design quality system — including design checklist delivery, silicon data analysis, and cross-team data collection framework — ensuring that silicon learnings are systematically captured and fed back into the project before the next generation design is finalized. The ideal candidate brings hands-on experience in design execution, simulation to silicon correlation, and cross-functional methodology development, and embraces AI-driven analysis and data-driven decision making to accelerate quality improvement cycles. Responsibilities will include, but are not limited to: High-speed IO design architecture for HBM products Define and standardize IO design quality process from architecture to silicon Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis Contribute to cross group communication to work towards standardization and group success Proactively solicit input from Standards, CAD, m

Who Are We HALA is a leading fintech player in the MENAP region that aims to redefine financial services and build the future bank of SMEs. HALA aims at empowering SMEs to start, run, and grow their businesses by providing them with cutting-edge financial and technological tools. HALA currently holds multiple entities in UAE, Saudi Arabia and Egypt (including HALA Payments and HALA Logistics) and offers solutions that enable merchants to digitize their payments as well as manage their sales and operations. Founded in 2017, HALA is currently licensed by the Saudi Arabian Central Bank. Objective: We are seeking a senior auditor to join our Internal Audit team and perform risk-based financial, accounting, and finance-related audits across HALA. The senior auditor will be responsible for planning and executing audits covering financial reporting, accounting processes, financial controls, treasury, revenue assurance, reconciliations, financial instruments, and other finance-related activities. The role involves evaluating the design and operating effectiveness of internal controls, assessing compliance with applicable regulatory requirements and accounting standards, identifying financial and operational risks, and providing practical recommendations to strengthen financial governance, reporting accuracy, operational effectiveness, and risk management. The position will also contribute to the execution of the approved Internal Audit Plan, development of audit methodology, supervision of audit resources, and delivery of high-quality audit reports and insights to senior management and the Audit Committee. Responsibilities: -Perform audit planning activities, including risk assessments, audit scoping, identification of key financial risks and controls, development of audit programs, and preparation of testing procedures -Evaluate the design and operating effectiveness of financial controls, identify control deficiencies, assess their financial and operational

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 200+ public data centers globally and thousands of private sites at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. Role We are looking for a Principal Software Development Engineer (Control-Plane) to join our Engineering team. This is a hybrid (in Santa Clara, CA office minimum 3 days per week) role, reporting to the Director, Software Development Engineering. We are expanding our existing control path and looking for a software engineer to help drive the development of new features and enhanced functionality. You will play a pivotal role in evolving our architecture to ensure it meets the demands of our growing user base. What you’ll do (Role Expectations) Define software design specifications and implement bug-free code using test-driven methodology and modern AI-based coding tools Design, develop, and optimize the system, including networking and security features, to support high-performance applications while performing unit testing and automation to ensure quality Apply strong software design principles and deep trou

Senior Software Engineer Mission Systems Software Developer Company: The Boeing Company The Boeing Company has an exciting opportunity for a Senior Software Engineer Mission Systems Software Developer (Level 5) to join Boeing Defense, Space & Security (BDS) in Daytona Beach, Florida . BDS is a global leader in the development, production, maintenance and enhancement of fixed-wing and rotary wing aircraft, commercial and government satellites, human spaceflight programs and weapons. Key markets include aeronautics, space and weapons. Core capabilities are in development, production and mission enabling upgrades of integrated solutions. BDS delivers the most digitally advanced, simply and efficiently produced and intelligently supported solutions to its customers. Daytona Beach is the company's newest state-of-the-art facility focused on engineering excellence. Florida offers no state income tax and a variety of other desirable personal and financial benefits. This position will include developing software and software tests throughout all phases of the software development life cycle (requirements, architecture, implementation, and verification). The software engineer will develop software in a Continuous Integration / Continuous Deployment (CI/CD) DevSecOps software build pipeline using an agile methodology focused on code quality, security and automation. Position Responsibilities: Develop Participates in use case development of software requirements Ability to lead activities to develop, document and maintain software architecture, requirements, algorithms, interfaces and designs for mission systems software Leads development of code and integration of complex Mission Systems softwar

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Department ADTS ATI PI Project Title Faster Cell Metrics Drift Detection Using Advanced Data Analytics Project Description The intern will undertake a structured engineering project to develop data analytics and detection models for the early identification of cell metric drift using large-scale manufacturing test and measurement data. Under the guidance of experienced engineers, the intern will analyze relationships among inline, probe, cell metric, and quality data. The intern will gain exposure to industrial data analytics, statistical analysis, detection modelling, and visualization techniques used in semiconductor manufacturing. The project may also involve AI-Enabled workflows for data exploration, pattern identification, and analytical productivity. Project activities will focus on defined analytical assignments and measurable learning outcomes. Objective of the Project Develop an understanding of cell metrics and their relationship with semiconductor manufacturing and product-quality data. Analyze manufacturing data to identify early indicators of cell metric drift. Develop a detection methodology for monitoring selected cell metrics and potential quality excursions. Communicate a

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Development and execution of alignment programs Develop and implement alignment programs with TPM core teams and task force teams across the network to drive BKM alignment and network standardization to improve efficiency and performance in each of the Pillars. For improvements in scale, identifying and driving improvements in Tool Utilization to meet BIC standards including elimination of low utilization tools in Micron, generation of globally aligned cold/warm idle shutdown of tools when not in need to generate OPEX and CAPEX savings, and resolving Tool POR-MOR gaps on major volume, with aligned BKMs implemented across the network & PDM updated. For Speed this will include execution of Early-Stage Transfer Alignment (ESTA) to drive BKM sharing between technologies, process recipe alignment and identification and alignment of BKMs to improve machine mismatch and defect performance. For Quality this will include alignment of PM Procedures, for shared workstations, Post Maintenance Qualifications, Scrap reduction and GDM recurrence prevention. For Cost this will include performing Power Walks to understand practices across the network and development of methodology and system improvements to drive labor efficiency and driving

Figma is growing our team of passionate creatives and builders on a mission to make design accessible to all. Figma’s platform helps teams bring ideas to life—whether you're brainstorming, creating a prototype, translating designs into code, or iterating with AI. From idea to product, Figma empowers teams to streamline workflows, move faster, and work together in real time from anywhere in the world. If you're excited to shape the future of design and collaboration, join us! Figma’s Data Science team partners across product, engineering, design, marketing, sales, and operations to help Figma make better decisions with data. As a PhD Data Science Intern, you’ll bring rigorous research training to some of Figma’s most important and open-ended questions, from researching emerging product and user behaviors and Figma’s broader ecosystem to developing new measurement methodologies, applying causal inference or machine learning, and building analytical systems. You’ll own a data science project end-to-end: from framing the question and methodology to translating findings into insights that influence Figma’s products, strategy, or data science practices; with the potential to continue toward publication after the internship. This internship will be based out of our San Francisco or New York hub. What you’ll do at Figma: Partner with cross-functional teams to turn ambiguous product, platform, or business questions into well-defined data science problems Analyze user, product, or business data to uncover insights and recommend actions Design and evaluate experiments, metrics, statistical or machine learning models, and analytical frameworks Communicate assumptions, tradeoffs, limitations, and recommendations clearly to technical and non-technical partners Own a focused internship project end-to-end, from problem framing and technical execution through final recommendations, with potential to continue toward publication after the internship We’d love to hear from you if you h

Who are we? Cohere is the leading security-first enterprise AI company. We build cutting-edge foundation AI models and end-to-end products that are designed to solve real-world business problems. We’re training and deploying frontier models for enterprises who are building AI systems. We believe that our work is instrumental to the widespread adoption of AI and we are looking for folks that want to be part of that. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. Cohere is a team of researchers, engineers, designers, and more, who are all passionate about their craft. We are a global technology company headquartered in Toronto with key offices in London, New York City, San Francisco, Montreal, Paris, Berlin and Seoul. Join us! About The Role Help bring Cohere's enablement strategy to life for our field teams in EMEA. This generalist role will build and manage programs end-to-end, from design through rollout, measurement, and iteration, while working directly with managers and reps to ensure enablement drives results. You'll report to the Head of Sales Enablement and help establish operational rigor as this global function scales. Key Responsibilities Own enablement programs from design through rollout, measurement, and iteration Partner with Product, Marketing, Sales Leadership, and RevOps to align GTM priorities and embed enablement into every stage of the sales lifecycle Create and curate high-impact resources (playbooks, battle cards, demo scripts, certification programs) for Cohere's solutions Establish KPIs (win rates, sales cycle efficiency) and use analytics to refine initiatives and prove ROI Operationalize MEDDPICC methodology into everyday seller behavior (deal reviews, coaching, planning) Build certification paths that accelerate new seller productivity across regions and cultures Maintain and evolve the enablement content platform to ensur

Our Purpose Mastercard powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title and Summary Senior Auditor Overview: Mastercard's Global Internal Audit team provides independent and objective assurance and advisory services to assess and enhance the effectiveness and efficiency of governance, risk management, and internal control processes. The team is seeking a Senior Auditor based in Pune, India, to support financial, operational, regulatory, and technology audit and advisory engagements. The ideal candidate is initiative-taking, intellectually curious, analytical, meticulous, and able to balance independent delivery with effective collaboration across a global team. Role: • Execute financial, operational, regulatory, technology, and advisory audits across business lines in accordance with Internal Audit methodology and quality standards. • Participate in audit planning, including understanding business processes, assessing risks, contributing to scope and approach, and developing audit procedures. • Independently evaluate the design and operating effectiveness of controls, document high-quality workpapers, and communicate testing status, potential issues, and delivery risks on a timely basis. • Identify control gaps, root causes, and process improvement opportunities; develop practical recommendations that address underlying risks and support sustainable remediation. • Draft

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) team at Micron is shaping the future of memory and storage technologies that fuel the AI era. We collaborate with global R&D groups, suppliers, and manufacturing teams to turn bold ideas into production-ready solutions. We innovate fast, learn continuously, and work as one team! This position is intended to be part of Micron's Technical Leadership Program (TLP). This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Position Overview: We are seeking an experienced organizational leader who will l ead and influence methodology improvements, including best practices in process development, data-driven decision-making, and application of AI/advanced analytics to drive innovation. In this role, you will drive strategic process development for Micron’s most advanced memory products, including HBM, 3DS DRAM, and emerging 3D architectures. You will guide end‑to‑end technology execution, partner across organizations, and influence both internal roadmaps and the external ecosystem. This is a high-impact role for someone who thrives at the intersection of innovation, complexity, and collaboration. Responsibilities: Own advanced packaging process technologies across wafer‑level and die‑level modules from pathfinding through manufacturing readiness Develop