Node Development Product Engineer Jobs

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Ready to do the most impactful work of your career? At Coinbase , we are uncompromising on our mission to increase economic freedom. The bar is high, the environment is intense, and we like it that way. This isn't a place for complacency, it’s a place to be pushed past your perceived limits. If you're ready to build the future of finance alongside people who refuse to settle for "good enough," you belong here. Coinbase is a remote-first, but not remote-only company. Expect to get together quarterly for intense in-person working sessions called “surges.” learn more about working at Coinbase . We're hiring a Senior Software Engineer to join the CB Node team within the Platform organization. This team runs all the blockchain nodes that power every asset Coinbase offers to customers, currently spanning 55 unique protocols across Ethereum, Bitcoin, Solana, and beyond. You'll focus on performance optimization and reliability across the blockchain platform stack, diagnosing root causes instead of over-provisioning, reducing infrastructure spend, and building the observability and health-check systems that keep our nodes reliable at scale. What you'll do: Own deep performance analysis and optimization across the blockchain node stack, diagnosing root causes of resource consumption and implementing system-level fixes that reduce infrastructure spend while maintaining reliability SLOs. Build observability, health-check, and automated failover capabilities for blockchain nodes, ensuring the team can detect degradation and respond proactively rather than reactively scaling resources. Drive a right-sizing initiative across the node fleet, profiling workloads, identifying over-provisioned instances, and establishing capacity models that balance cost efficiency with headroom for reliability. Partner with protocol integration engineers, wallet teams, and indexer teams to extend performance improvements across the full blockchain platform stack, not just the node la

Ready to do the most impactful work of your career? At Coinbase , we are uncompromising on our mission to increase economic freedom. The bar is high, the environment is intense, and we like it that way. This isn't a place for complacency, it’s a place to be pushed past your perceived limits. If you're ready to build the future of finance alongside people who refuse to settle for "good enough," you belong here. Coinbase is a remote-first, but not remote-only company. Expect to get together quarterly for intense in-person working sessions called “surges.” learn more about working at Coinbase . We're hiring a Software Engineer to join the CB Node team within the Platform organization. This team runs all the blockchain nodes that power every asset Coinbase offers to customers, currently spanning 55 unique protocols across Ethereum, Bitcoin, Solana, and beyond. You'll contribute to performance optimization and reliability across the blockchain platform stack, diagnosing root causes instead of over-provisioning, reducing infrastructure spend, and building the observability and health-check systems that keep our nodes reliable at scale. What you'll do: Own performance analysis and optimization tasks across the blockchain node stack, diagnosing root causes of resource consumption and implementing system-level fixes that reduce infrastructure spend while maintaining reliability SLOs. Build observability, health-check, and automated failover capabilities for blockchain nodes, ensuring the team can detect degradation and respond proactively rather than reactively scaling resources. Execute right-sizing improvements across the node fleet, profiling workloads, identifying over-provisioned instances, and contributing to capacity models that balance cost efficiency with reliability. Partner with protocol integration engineers, wallet teams, and indexer teams to extend performance improvements across the blockchain platform stack. Support the definition and implementati

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks General Expectations: Contribute to group objectives and drive projects with limited supervision. Continuously evaluate and refine approaches and goals. Implement and transfer processes across teams and sites. AI adaptation such as u sing Artificial Intelligence, applying Artificial Intelligence to daily tasks and create Intelligence agents to aid projects Specific Expectations: Define reticle specifications in collaboration with MTC for each node series. Ensure fracture teams apply best-known methods and correct misuse of techniques. Support tapeout teams in implementing new data preparation flows. Evaluate long-running fracture jobs that do not meet performance goals. Fulfill internal reticle material requests using standard production flows. Troubleshoot CD Metrology issues prior to OPC production handoff. Resolve integration issues using OPC procedures and identify recipe/process interactions. Provide feedback to OPC management for innovative improvements. Mentor peers by sharing hands-on knowledge beyond standard training. Deliver quality, timely results for significant projects with high impact. Foster positive interactions with team members, other departments, and suppliers. Ownership and Continuous Improvement: Evaluate issues and implement improvements in toolsets or pr

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes. Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets. Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout. Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage sc

What We’re Looking For: We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort. Ideal Candidates: Ideal candidates will have: Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them Experience both with in-house and outsourced physical design flows Nice to Have: Experience with physical design process for multi-die/multi-chiplet/MCM designs Experience with physical design process for reticle-max or near reticle max designs Experience with very high power density chips Experience with the physical design process for AI chips Experience with the physical design process of analog and mixed signal blocks and macros

What We’re Looking For: We’re looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products. Ideal Background: An ideal candidate will have: Experience leading the architecture of an entire system or subsystem (eg chip, board, die, package) Deep understanding of AI workloads like LLM inference at workload levels and its system level implications Experience with large multicore architectures Nice to Have: Experience with physical design process of large-die area, advanced node chips Experience with multi-die designs such as MCMs and interposer designs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities & Skills Minimum 7 years of hands-on experience in Oracle Database Administration and production support environments. Strong experience administering Oracle Database 19c and exposure to Oracle 26ai. Perform Oracle database installations, upgrades, migrations, cloning, refresh activities, and patching using Release Updates (RU), one-off patches, and Grid Infrastructure patches. Strong understanding of Oracle RAC architecture with hands-on experience supporting 2-node, 3-node, 4-node, and 5-node RAC clusters. Expertise in troubleshooting Oracle Clusterware, OCR, Voting Disk, ASM, RAC services, SCAN listeners, and Grid Infrastructure-related issues. Extensive experience in Oracle RMAN backup and recovery strategies, including backup validation, restore and recovery operations, Point-in-Time Recovery (PITR), and disaster recovery testing. Strong expertise in Oracle performance tuning and troubleshooting, including SQL tuning, execution plan analysis, AWR, ASH, and ADDM report analysis. Ability to diagnose and resolve CPU, memory, storage, I/O, network, and operating system-related database performance issues. Strong Oracle ASM administration experience, including ASM disk group management, troubleshooting, rebalancing activities, storage optimization, capacity planning, and performance analysis. Extensive hands-on experience with Oracle Data Pump exports/imports, schema migrations, database refreshes, full database mig

What We’re Looking For: We’re looking for great analog and mixed signal circuit designers to join us in contributing to the design of our production optical PHY. Ideal Background: Ideal candidates will have: Deep knowledge, hands on experience and multiple successful tapeouts with advanced node analog and mixed signal circuit designs Deep knowledge, hands on experience and multiple successful tapeouts of high speed communication link Tx and/or Rx circuits Nice to Have: Understanding of PHYs and how analog components and circuits integrated into the broader PHY system Understanding and hands-on experience with clock-forwarded links, especially clock-forwarded optical links Design and successful tapeout experience with optical links, either on Tx or Rx sides Design and successful tapeout experience with AMS circuits for optical components

We’re looking for power integrity engineers to ensure that power is delivered and stable at all levels: rack/tray, package, die, core. Ideal Background: Experience with large die, high TDP chip PDN analysis and design Experience with advanced node (7nm and lower) chip PDN analysis and design Ability to work with package architects to determine best passives design within a given set of constraints Ability to work with ASIC and microarchitecture team to hit power integrity goals given manufacturing design constraints Nice to Have: Experience with WSI (wafer-scale integration) systems Board and system-level power delivery network analysis and design Low voltage die power delivery network analysis and design Many voltage domain power delivery network design and analysis IVR based design experience

About Us: AI needs a new infrastructure layer. We're building it at Modal. Every era of computing brought new workloads that previous infrastructure couldn't support: mainframes, databases, and the cloud. Each time, the company that rebuilt the layer underneath defined the decade. AI is no different, except it touches everything instead of one slice, and the window to build the layer underneath it is open right now. Our customers include category-defining companies like Ramp , Cognition, DoorDash, and Suno. They rely on Modal for instant GPU access, sub-second container starts, and native storage, so it's simple to serve low-latency inference, fine-tune models, and access production-ready sandboxes at scale. We've passed $1B in annualized run rate, up 15x from a year ago. In October 2026 we raised a $750M Series D led by Accel at a $15.75B valuation. Our team includes creators of popular open-source projects (e.g., Seaborn , Luigi ), academic researchers, international olympiad medalists, and experienced engineering and product leaders with decades of experience. The Role: We're building a platform that covers the whole life of an LLM: training it, deploying it, and observing it in production. We already run multi-node training, elastic inference, sandboxes, and distributed volumes, and we control the infrastructure underneath. We’re looking for research depth in post-training to sit alongside our systems and product work. What You'll Do: We are looking for research scientists with a strong track record in reinforcement learning, machine learning, and foundation models, including large language and multimodal models, to join our research team. This role is well suited to candidates interested in improving existing methods and developing new techniques for large-scale model training, optimization, and inference, extending models to long-context and long-horizon tasks, and improving inference-time efficiency, reliability, and robustness in high-stakes real-world deplo

About the Role In this role, you will operate, scale, and optimize multi-petabyte storage systems purpose-built for the world’s largest AI training and inference workloads. You’ll manage and scale high-performance parallel filesystems and object stores, evaluate and integrate cutting-edge technologies such as Vast, Weka, Ceph, and Lustre, and solve the complex engineering challenges of operating at extreme throughput, low-latency data paths, and massive cluster-scale storage operations. You will also build Kubernetes-native storage operators and self-service platforms that provide automated provisioning, strict multi-tenancy, performance isolation, and quota enforcement at cluster scale. Day-to-day, you’ll optimize end-to-end data paths for 10-50 GB/s per node, design multi-tier caching architectures, implement intelligent prefetching and model-weight distribution, and tune parallel filesystems for AI workloads. Responsibilities Architect and implement the technical strategy and storage roadmap for Together AI, driving high-performance architectural decisions as we scale our GPU fleet. Engineer and scale multi-petabyte AI/ML storage systems by integrating Vast, Weka, and Ceph while executing deep cost optimization through automated tiering and lifecycle policies. Develop intelligent caching and tiered storage architectures to achieve extreme IOPS and cluster-wide throughput at GPU scale for training and inference workloads. Tune storage isolation at the L2/L3 network layers to ensure secure, production-grade multi-tenancy for storage clients. Code Kubernetes storage operators and controllers to enable automated provisioning, self-service abstractions, and quota enforcement. Engineer end-to-end data paths to achieve 10+ GB/s per GPU node; architect multi-tier caching for model weights and datasets; tune parallel filesystems using advanced profiling; and scale storage infrastructure across thousands of nodes. Optimize end-to-end data paths through advanced

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The F15 ATE DIF Engineer is responsible for successful transfer achievement of new technode transferred from TD, Yield improvement/CT reduction/tool expansion toward TTMCY with great collaboration with TD/F15 all related Dept/DRAM network/MCT.Safety, Technology transfer to sister site & further new tech node transfer readiness are also our responsibility. As one of our team members, you should Understand site, department, area goals and set individual goals to achieve them with discussion with your SV. You are required to take a responsibility for process & workstation as owner and do all tasks assigned timely and accurately. You are also highly appreciated to work positively and show your ownership of all the tasks you are assigned. Responsibilities and Tasks: • Establish and improve process condition and technology. • Upgrade process capability and reduce production cost. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-perfor

Elastic, the Search AI Company, enables everyone to find the answers they need in real time, using all their data, at scale — unleashing the potential of businesses and people. The Elastic Search AI Platform, used by more than 50% of the Fortune 500, brings together the precision of search and the intelligence of AI to enable everyone to accelerate the results that matter. By taking advantage of all structured and unstructured data — securing and protecting private information more effectively — Elastic’s complete, cloud-based solutions for search, security, and observability help organizations deliver on the promise of AI. What is the Role You are the person a customer calls when their Elasticsearch platform is the problem, or when they need one designed properly the first time. That means you decide the shape of a cluster and then defend that decision — node topology, shard strategy, data tiers, lifecycle and retention — with the sizing arithmetic to back it up. It also means you can follow a performance problem beyond Elastic itself. We need someone whose instinct is to look down the stack and sideways to whatever else shares the infrastructure, rather than stopping at the cluster API. What You Will Be Doing Design and build Elasticsearch platforms for customers across self-managed, orchestrated and managed deployments, including air-gapped and regulated environments Own sizing and capacity planning as a derivation from workload characteristics — ingest rate, document shape, retention, query concurrency, growth — validated by benchmark rather than estimated from a form Run health checks and remediation on production estates, and redesign sharding, mapping and index strategies where the original design no longer holds Lead major-version upgrades, snapshot and disaster recovery strategy, and multi-cluster architectures Diagnose performance problems across the full stack — Elastic, the JVM, the operating system, storage and network — and across adjacent systems in t