Packaging Artwork Design Assistant Jobs

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As FE CPIE CPI PI Senior Engineer at Micron Technology, Inc., you will be responsible for working with global Micron network to drive each silicon node's Packaging Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution. In addition, you will be responsible in integrating solutions by connecting cross-functional expertise, standardizing the business process and regularly benchmarking internal and external intelligence to achieve the highest value bits and productivity. In addition, you will leverage AI-enabled engineering approaches, advanced analytics, and digital tools to accelerate problem solving, improve productivity, enhance decision quality, and drive continuous innovation across product yield, quality, and business processes. Responsibilities and Tasks Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering. Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualific

About the role The Customer Success Manager - Growth and Retention is responsible for reducing churn, improving customer health, and protecting recurring revenue through early risk detection, cross‑functional mitigation, and scalable retention programs. The role partners closely with Renewals, Customer Success, Customer Engagement, Competitive Intelligence, and Pricing & Packaging to orchestrate coordinated customer‑save strategies. This role also provides renewal objection handling expertise , enabling teams to navigate downsells, downgrades, competitive threats, pricing pushback, TCO/ROI concerns, and budget constraints. The ideal candidate excels at influencing cross‑functional teams, handling commercial risk, and translating customer insights into save actions. What you’ll do 1. Churn Risk Identification & Health Intelligence Maintain a standardized customer risk scoring framework leveraging health signals, product usage, support patterns, sentiment, and competitive exposure. Identify early risk indicators (e.g., discount cliffs, adoption gaps, under-deployed licenses, sponsor turnover). Partner with Renewal Ops, Data team to automate risk workflows in Salesforce Collaborate with Competitive Intelligence to map competitive displacement trends and update counter strategies. 2. Cross‑Functional Risk Orchestration (Renewals, CS, CI, Pricing) Lead weekly renewal risk reviews/war rooms with Renewals, CSMs/CEMs, and Sales to align on mitigation actions. Build account-level mitigation plans that include adoption interventions, executive alignment, value reinforcement, and commercial flexibility. Partner with Pricing & Packaging and Deal Desk to design controlled commercial offers (e.g., term/ramp, New Product Introductions, New SKU Impact, Product Bundling etc). Escalate systemic product, billing, or support issues and track resolution. 3. Renewal Objection Handling Serve as the subject‑matter expert for Renewals by providing guidance, playbooks, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs! We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM). If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you! Responsibilites: Lead Co-Design from Silicon to System - Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development - Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM - Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/D

We Creative Zone, We print high-quality RFID cards for offices, schools, colleges, hotels, hospitals, apartments, gyms, and businesses. Our durable PVC RFID cards are compatible with most access control and attendance systems, offering excellent print quality, long-lasting performance, and professional finishing. Services Offered RFID Smart Card Printing Premium PVC RFID Cards Attendance Cards Hotel Key Cards Access Control Cards Custom RFID Card Printing Why Choose Us? Professional Design Support | Competitive Prices Quick Production | Reliable Quality Secure Packaging | Online Ordering Excellent Customer Support https://www.instagram.com/creativezoneidcards/ https://www.facebook.com/share/1BFV59CmYh/ Contact: MULLAI 501 Creative Zone –Bangalore

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the Technology Development — Advanced Modeling & AI Solutions (AMAIS) organization, you will be part of a multidisciplinary team developing next-generation Digital Twins, predictive modeling solutions, and AI-driven technologies that accelerate advanced memory development and manufacturing excellence. You will create predictive digital representations of semiconductor processes, materials, structures, equipment, and products across DRAM, NAND, and advanced packaging technologies including HBM. Leveraging physics-based modeling, computational methods, machine learning, GenAI, large language models (LLMs), and agentic AI frameworks, you will enable technology co-optimization, design-space exploration, process optimization, yield improvement, and accelerated technology learning. Working at the intersection of engineering fundamentals, manufacturing data, and digital engineering, you will develop scalable predictive and prescriptive solutions that connect process, structure, performance, yield, reliability, and cost. This role offers the opportunity to influence critical technology decisions, drive fab-technology co-optimization , and advance Micron's leadership in data-driven semiconductor memory innovation. Qualifications: Independence – be comfortable executing activities and needs Experience in algorithm development, numerical methods, and scientific computing Solid experience with Plasma, FPM, HAR etching, and MC modeling Experience with Wet Pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: A senior advanced assembly technology development engineer is responsible for introducing new technology to enable next generation packaging. This position engaged latest stacking/flip chip technology, advance packaging material and work on new process set up, process/ packaging characterization and process transfer from TD phase to high volume production to meet development milestone. This position required high motivation and operation skill to build DOE sample and fulfill customer requirement sample as well as cooperate with Material engineer, Bumping, PI, NPI, quality and manufacturing team to ensure process transfer successfully. Responsibilities Explore new technology on semiconductor industry such as flip chip, TCB and hybrid bonding process equipment and packaging material. Provide plan and resource requirement to enable new technology. Set up DOE plan and execute. Build sample and perform data analysis skill. Lead efficiency trouble shooting skill to improve process. Prepare documentation for process transfer from TD to HVM Review process stability by FDC, SPC and test result. Self-motivated and capable of working independently, proactively identifying opportunities and driving projects with minimal direction. <span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry. As a Realtime Defect Analysis (RDA) Technology Development Engineer in APTD, you will learn how to use pioneering defect detection equipment and processes to solve issues and drive improvement. The goal of this position is to accelerate cycles of learning and technology transfer in Technology Development (TD). We're seeking an engineer who is passionate about creative problem solving and finding innovative solutions. This position will provide the opportunity for you to collaborate with engineers in process integration, process development, data science, and yield analysis within and outside of TD. Your ideas will impact the team globally! We need someone who will investigate process anomalies through root-cause analysis, data manipulation, and correlations. You will be expected to support experimentation, data analysis, baseline health metrics, and systema

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of APTD SG Technology Development Process Integrator, you will be responsible for developing advanced packaging process solution and ensure New Process, New Equipment, New Material and Path finding activities success for all adv pkg products in Micron. To lead new Technode process readiness and improving the yield, quality and reliability with process characterization and optimization and new materials, machines & technologies introduction. You will need to have understanding of Frontend Process, packaging requirements, chip package interaction, equipment understanding and process technology in the industry. The ability to enable best technology for New Technode with packaging requirements. You will also be required to drive & collaborate with cross functional teams to resolve process related problems. Ensure smooth transition from new process development, 1st qualification success to small volume production launch Development and Qualification of new packaging process, material, equipment and technology solutions to meet new Technode requirements and schedule Perform CPI NUDD, process TRA, risk mitigation execution and process recipe readiness prior Silicon arrives and ensure 1st pass rate. Qualify new process/technology/equipment/materials Technical capability Identify path finding opportunities for Micron's technology leadership with BIC time to market, continuou

SYNOPSIS: The Manufacturing Co-Op role is designed for high school juniors and seniors seeking entry-level experience in production. As a Co-Op, you will perform various tasks associated with assembly, ensuring the quality of your work. This position offers the flexibility to work in teams, small batch production, or flow lines. This opportunity aims to provide valuable hands-on experience in production, with the potential for future apprenticeship opportunities. Projected start date: Fall 2026 RESPONSIBILITIES: May be required to operate various hand tools and other equipment. Has the ability to read and understand production documentation and drawings. Understands basic electronics concepts and can follow wiring schematics. Performs final assembly, electrical testing, and packaging of various assemblies Performs screening and separation of various parts Responsible for recording assembly time data and completion of all associated routing, quality inspections, and other related forms Performs miscellaneous assigned tasks Assist in other Production areas as needed Focus on increasing productivity in all activities Follow necessary PPE requirements, appropriate ISO specifications and company procedures. Performs other related duties as assigned. QUALIFICATIONS: Must be a junior or senior in high school. Must be at least 16 years of age by the start of the role. Strong organizational skills. Ability to read and comprehend English written production documents. Basic computer skills. Consistently demonstrate a positive attitude toward all aspects of work Apply effort and energy to lifelong learning and strive to continually grow Knowledge of and desire to work in a production environment. ESSENTIAL JOB FUNCTIONS: Must be willing to be cross trained in several assembly functions to meet constantly changing production requirements Must be willing to be moved into various work centers in order to meet production requirements or where skills best serve departm

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Technology Development (TD) department at Micron Technology leads innovation. It drives the advancement of data retention and storage systems that change how the world uses information. The team develops next-generation semiconductor processes and technologies and works closely with global R&D and manufacturing teams to bring innovative solutions from concept to production. Join a collaborative environment where you will help shape the future of semiconductor technology while working alongside experienced engineers and technical leaders. Position Overview As a Process Integration Engineer in Advanced Packaging Technology Development (APTD), your role includes developing advanced packaging approaches and linking technologies. You will contribute to their integration in future semiconductor products. Working in a highly collaborative R&D environment, you will support process development, technology evaluation, and qualification activities while gaining hands-on experience with modern semiconductor technologies. This role provides an excellent opportunity for engineers who are passionate about innovation, problem-solving, and continuous learning. Responsibilities Support the development, characterization, and integration of groundbreaking packaging and interconnect solutions for next-generation semiconductor products. Collaborate with multi-functional engineering teams to analyze process data, solve technical challenges, and improve technology performance. Participate in e

About the job Build the test strategy that protects Graphcore’s system software releases at scale. As a Staff System Software Engineer, you will shape integration and system testing across firmware, BMC and Linux device drivers. Your work will help create a high quality gate for system software release packages. You will design, build, automate and report tests across complex server class systems. You will also develop reusable tools, pipelines and packaging solutions that help teams move faster with confidence. This role needs deep low level software knowledge and strong system thinking. You will own hard technical areas, guide best practice and stay close to the code. The team and culture You will join a new integration and system test team within System Software QA. The team verifies integrated components across BMC, firmware and Linux device drivers. Work happens close to the hardware, across component teams and QA. You will partner with developers, consult package stakeholders and turn use cases into robust system tests. Decisions are shaped by evidence, clear technical reasoning and ownership. You will be expected to speak up, act fast and raise standards through hands-on leadership. What we’re looking for · Strong experience in low level system testing and integration across complex software and hardware layers. · Deep understanding of RTOS, complex boot logic, Linux and device drivers. · Test development capability using Python and C/C++. · Experience working with hardware, debuggers, CI/CD pipelines and build or integration tools. · Ability to debug cross-layer issues and drive root-cause investigations to lasting corrective actions. · Clear communication skills, with the ability to mentor engineers and document complex technical decisions. While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background m