Packaging Engineer Jobs

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

About Scale AI At Scale, our mission is to develop reliable AI systems for the world's most important decisions. Our products provide the high-quality data and full-stack technologies that power the world's leading models, and help enterprises and governments build, deploy, and oversee AI applications that deliver real impact. Scale Frontier Data is the organization behind the training and evaluation data that frontier labs depend on. We build the systems, tooling, and expert workflows that turn hard human expertise into signals that models can learn from, across reasoning, coding, agentic tool use, and domain expertise. Reinforcement learning environments are now the center of gravity for that work: the difference between a model that demos well and a model that reliably completes long-horizon work is almost always the quality of the environments and reward signals it was trained against. Responsibilities As a Staff Software Engineer, RL Environments, you'll own the technical foundation for how Scale builds, runs, verifies, and delivers RL environments at scale. An RL environment is a real piece of software: a containerized world with real dependencies, real state, real tools, and a grader that has to be correct even when the agent is creative about breaking it. Building one is a full-stack engineering problem. Building thousands of them reproducibly, cheaply, with trustworthy reward signals and throughput measured in millions of rollouts is a systems problem that very few people have solved. You'll work on both. You'll design the platform: sandboxed execution, environment packaging and versioning, rollout orchestration, trajectory capture, verifier frameworks, and the authoring surfaces that let engineers and domain experts produce environments without reinventing infrastructure each time. And you'll go deep on the environments themselves by instrumenting real applications, designing task suites that expose specific capability gaps, and building graders that

Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we’re looking for exceptional talent to reimagine the way the world works. Senior Mechanical Engineer — Robotics Hardware Location - Bangalore Instawork Robotics Labs is building Instacore, our proprietary five-camera and IMU wearable capture rig. Hundreds of units operate across India every day, collecting real-world data used to train frontier Physical AI models. We are looking for a senior, mechanically focused engineer to own the complete hardware lifecycle for Instacore and future hardware products. This person will independently lead design, prototyping, manufacturing, testing, deployment, logistics, maintenance, and continuous improvement. What you’ll do - Own the mechanical design and development of Instacore and other robotics hardware from initial requirements through production and field deployment. - Create detailed CAD models, assemblies, engineering drawings, bills of materials, and manufacturing documentation. - Rapidly prototype and validate designs using 3D printing, machining, fabrication, and off-the-shelf components. - Design durable mounts, enclosures, fixtures, wearable components, packaging, and protective systems. - Own design for manufacturability, assembly, serviceability, reliability, and cost. - Improve cable routing, connector retention, strain relief, thermal management, ingress protection, and resistance to vibration and impact. - Design packaging and logistics processes that prevent damage during storage and transit. - Establish verification, stress-testing, quality-control, and acceptance-testing procedures. - Investigate field failures, d

EMPLOYER IS A CONTRACTOR FOR THE U.S. GOVERNMENT. Role Description We are seeking a talented Sr. Platform Engineer to join the Navy Delivery team. This role sits at the intersection of platform engineering, application development, DevOps, and application security. The ideal candidate will help application development teams successfully integrate, package, secure, deploy, and operate their software on the Unicorn Delivery Service (UDS) and Kubernetes-based environments. The successful candidate will understand both sides of the application/platform boundary. They should be comfortable working with application source code, APIs, containers, CI/CD pipelines, Kubernetes resources, Helm charts, and production runtime concerns. They will collaborate directly with application teams to understand how their software is built and operated, translate those needs into repeatable deployment artifacts and processes, and identify issues across application and platform layers. Experience developing or supporting modern web applications and APIs is particularly valuable. Current application teams use technologies including React, Vue, NGINX-hosted static assets, C#/.NET services, and Python/FastAPI services. Direct experience with every technology is not expected; we are looking for engineers who can quickly understand unfamiliar application architectures and help teams adapt them for secure, reliable deployment. As a Platform Engineer within our organization, you will join a team of dedicated unicorns focused on advancing freedom and independence globally. Our teams work across different technical baselines depending on the engagement. Although our products primarily operate at the platform layer, delivering successful outcomes for our Heroes also requires us to work closely with application teams on CI/CD components, runner deployments and maintenance, UDS packaging, Kubernetes and Helm configuration, application observability, security controls, and process automation. Res

About Supabase Supabase is the Postgres development platform, built by developers for developers. We provide a complete backend solution including Database, Auth, Storage, Edge Functions, Realtime, and Vector Search. All services are deeply integrated and designed for growth. About the Role We’re looking for a Postgres Deployment Engineer to join our PostgreSQL team and help elevate our PostgreSQL offerings. You’ll work closely with the PostgreSQL team, playing an instrumental role in technical decision-making and refining internal methodologies. This role is ideal for someone who thrives in async, fast-paced environments and is excited about building developer tools that scale to millions. The focus of this role is owning the stability and deployment of our products. You will act as a bridge between product and infrastructure teams to improve the reliability of deployments and upgrades. You will have co-responsibility for builds and deployments via our public supabase/postgres GitHub repository, which bundles features into Docker images and AWS AMIs for cloud and local use. What You’ll Be Responsible For Package software into our supabase/postgres repo using Nix (with flakes), and help us transition our packaging from traditional to Nix packaging more over time. Manage PostgreSQL lifecycles, ensuring timely major, minor, and extension upgrades. Expand platform release systems to allow developers to increasingly self-service. Optimize CI/CD and tooling, specifically expanding GitHub Actions, team tooling, and testing/release approaches. Resolve production issues by proactively identifying and fixing problems in customer deployments. Maintain best practices and tests to ensure enhanced stability and decreased deployment risks. You Might Be a Good Fit If You Have 3+ years of experience with PostgreSQL and its ecosystem, including extensions and performance optimization. Are an Infrastructure Expert with proven experience in management, tooling, and optimization. Are p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs! We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM). If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you! Responsibilites: Lead Co-Design from Silicon to System - Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development - Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM - Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/D

About the Team Our Robotics team is focused on unlocking general-purpose robotics and pushing towards AGI-level intelligence in dynamic, real-world settings. Working across the entire model stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the constraints of physical systems to improve peoples’ lives. About the Role We are seeking a Senior Actuator Design and Integration Engineer to lead the development of custom electromechanical actuators for advanced robotic systems. You will own actuator development from early architecture and concept generation through prototype validation and system integration, partnering closely with mechanical, electrical, controls, firmware, reliability, and manufacturing teams. This role focuses on the design, integration, and validation of precision electromechanical systems, including motors, transmissions, sensing, structural components, and thermal architectures. You will help drive actuator development across the full engineering lifecycle while establishing scalable design, test, and integration practices for future robotic platforms. This role is based in San Francisco, CA, and requires in-person presence 4 days a week. In this role, you will Lead the architecture, design, and integration of custom robotic actuators, including motors, transmissions, sensing, thermal systems, structural components, and packaging. Define actuator requirements and system-level trade studies around torque density, bandwidth, efficiency, thermal performance, backdrivability, inertia, reliability, manufacturability, and cost. Design precision electromechanical assemblies with strong attention to tolerances, alignment, load paths, thermal expansion, sealing, wear, and serviceability. Drive actuator integration into robotic systems, partnering closely with controls, firmware, electrical, and robotics software teams to optimize closed-loop pe

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: A senior advanced assembly technology development engineer is responsible for introducing new technology to enable next generation packaging. This position engaged latest stacking/flip chip technology, advance packaging material and work on new process set up, process/ packaging characterization and process transfer from TD phase to high volume production to meet development milestone. This position required high motivation and operation skill to build DOE sample and fulfill customer requirement sample as well as cooperate with Material engineer, Bumping, PI, NPI, quality and manufacturing team to ensure process transfer successfully. Responsibilities Explore new technology on semiconductor industry such as flip chip, TCB and hybrid bonding process equipment and packaging material. Provide plan and resource requirement to enable new technology. Set up DOE plan and execute. Build sample and perform data analysis skill. Lead efficiency trouble shooting skill to improve process. Prepare documentation for process transfer from TD to HVM Review process stability by FDC, SPC and test result. Self-motivated and capable of working independently, proactively identifying opportunities and driving projects with minimal direction. <span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Technology Development (TD) department at Micron Technology leads innovation. It drives the advancement of data retention and storage systems that change how the world uses information. The team develops next-generation semiconductor processes and technologies and works closely with global R&D and manufacturing teams to bring innovative solutions from concept to production. Join a collaborative environment where you will help shape the future of semiconductor technology while working alongside experienced engineers and technical leaders. Position Overview As a Process Integration Engineer in Advanced Packaging Technology Development (APTD), your role includes developing advanced packaging approaches and linking technologies. You will contribute to their integration in future semiconductor products. Working in a highly collaborative R&D environment, you will support process development, technology evaluation, and qualification activities while gaining hands-on experience with modern semiconductor technologies. This role provides an excellent opportunity for engineers who are passionate about innovation, problem-solving, and continuous learning. Responsibilities Support the development, characterization, and integration of groundbreaking packaging and interconnect solutions for next-generation semiconductor products. Collaborate with multi-functional engineering teams to analyze process data, solve technical challenges, and improve technology performance. Participate in e

The Language Tools team enables ~1,500 Datadog developers to build, test, and package millions of lines of Go, Python, Java, Rust, and TypeScript in our backend monorepo. Our success is measured by their productivity and satisfaction. They use the tools that we develop and support several times a day, in both development and CI environments. We use the Bazel open source build system as a foundation. The team is growing rapidly, both with Datadog and as we absorb other repositories into the monorepo. As a senior software engineer on the team, you will own projects from start to finish, both greenfield and brownfield. You will gain first-hand understanding of what Datadog developers need, and inform our roadmap. At Datadog, we place value in our office culture - the relationships that it builds, the creativity it brings to the table, and the collaboration of being together. We operate as a hybrid workplace to ensure our employees can create a work-life harmony that best fits them. What You’ll Do: Invent build, test and packaging tools that are simpler and more reliable to use. Push performance and cost efficiency at scale, raising cache hit rates and cutting CI times and compute spend across millions of targets. Treat CI like SREs treat prod, making sure our pipelines are green and fast. Prepare, run, and finish complex migrations. Contribute back to the Bazel ecosystem, upstreaming fixes and shaping features we depend on. Who You Are: An expert in Bazel and/or one of the languages listed above. A well-rounded engineer. You must broadly understand the various types of software projects that are built, tested, and packaged with our tools. Both careful and fearless. The changes we make impact the velocity of hundreds of engineers. They are risky but necessary. User-focused. We help Datadog engineers to use the tools that we develop, and continuously improve their usability, so they don’t need our help the next time. Ideally, you have ex

Why Join The Drata Team? The best way to understand the Driver’s Mindset is to see it in action. We’re an award-winning, mission-driven team of 600+ people worldwide , united by a culture that values trust, speed, and continuous growth. Hear the Voice of the Team : Explore our "Life at Drata" page for employee testimonials on our collaborative and the growth opportunities available. Connect with Us on Socials: LinkedIn - follow us for company updates, employee stories, and career news. Job Summary: The Staff Software Engineer, Monetization Platform serves as a technical leader with a primary focus on the systems that turn product usage, subscriptions, credits, commitments, and contracts into accurate customer outcomes and clean financial operations. This person will architect and evolve the core billing domain for Drata: usage event ingestion, billable metrics, pricing and packaging, invoice generation, entitlement enforcement, and the integrations that connect engineering to Accounting, Finance, RevOps, Salesforce, CPQ, and ERP systems like NetSuite. They should be equally comfortable designing event-driven systems, shaping commercial flexibility with business stakeholders, and building operationally trustworthy software where correctness, audit-ability, and scale matter. Modern billing is no longer just “charge a credit card once a month” — it is a real-time product control plane that must support evolving pricing models without turning the codebase into a fragile mess. What you’ll do: Partner with Product, Finance, Accounting, RevOps, and Engineering leadership to shape Drata’s long-term billing architecture and commercial flexibility across self-serve and enterprise motions. Design the primitives of a modern billing platform: usage events, billable metrics, products, rate cards, contracts, credits, subscriptions, overages, and invoice workflows. Architect a system that can accurately meter product usage at scale, transform raw events into billable quantities, an

This position is responsible for supervising Nivagen label control and packaging area. Works in SAP system and Quality system to perform inspection testing of incoming labelling and packaging components. Supervising the packaging team to provide oversight of Packaging and making sure that AQL’s support finished product release. The position is a liaison with the warehouse, customer service and manufacturing for incoming goods both finished product and incoming components. The position is responsible for implementing Nivagen inspection and testing quality standards for labelling and incoming packaging components, while leading the packaging QA team to meet Nivagen timelines. ESSENTIAL DUTIES AND RESPONSIBILITIES Manage the Label Control Program ensuring that finished product is appropriately labeled to the correct versions and timelines. This includes management of specifications, inspections, and release of labelling in SAP. Manage the Packaging Component Specification program by obtaining documentation for components that have product contact from project managers, engineers, or purchasing. Prepare or review change controls to introduce product/components into Nivagen Quality System. Develop quality inspection criteria for finished products to include label review, temperature requirements, and destructive testing for quality attributes, if applicable. Create documentation for Quality inspection of each packaging component against supplier drawings, supporting documentation and physical testing. Work with Engineer and Operations for component acceptability testing on the line in conjunction of writing component specifications for approval. Sample and inspect incoming drug products and/or components against quality standards. Record and review documentation for accuracy and completeness. Maintain the initial and final documentation in the electronic management system. Disposition of product/component after quality review of inspection criteria Set up metadata in SAP

About the job Build the test strategy that protects Graphcore’s system software releases at scale. As a Staff System Software Engineer, you will shape integration and system testing across firmware, BMC and Linux device drivers. Your work will help create a high quality gate for system software release packages. You will design, build, automate and report tests across complex server class systems. You will also develop reusable tools, pipelines and packaging solutions that help teams move faster with confidence. This role needs deep low level software knowledge and strong system thinking. You will own hard technical areas, guide best practice and stay close to the code. The team and culture You will join a new integration and system test team within System Software QA. The team verifies integrated components across BMC, firmware and Linux device drivers. Work happens close to the hardware, across component teams and QA. You will partner with developers, consult package stakeholders and turn use cases into robust system tests. Decisions are shaped by evidence, clear technical reasoning and ownership. You will be expected to speak up, act fast and raise standards through hands-on leadership. What we’re looking for · Strong experience in low level system testing and integration across complex software and hardware layers. · Deep understanding of RTOS, complex boot logic, Linux and device drivers. · Test development capability using Python and C/C++. · Experience working with hardware, debuggers, CI/CD pipelines and build or integration tools. · Ability to debug cross-layer issues and drive root-cause investigations to lasting corrective actions. · Clear communication skills, with the ability to mentor engineers and document complex technical decisions. While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background m

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo