Pi Mb And Espec Engineer Jobs

About the Role We are a small team of AI builders in Paytm Labs. As a Staff AI Platform Engineer, you will work across inference and agentic systems. You will contribute to Paytm's AI inference platform (Pi), serving internal teams and enterprise customers - running our own coding and domain-specific models (voice, vision, risk, fintech workflows) as well as third-party models. You will also architect and build the platform that enables autonomous AI agents to operate safely and reliably in production - the runtime, orchestration, and developer tooling for agents to reason, plan, use tools, and execute complex multi-step workflows, automating both software development and business processes. You will work at the intersection of LLMs, distributed systems, and production fintech infrastructure, helping define how inference and agentic AI are built and deployed across payments, risk, fraud, collections, support, and developer experience. What You'll Do Inference & Model Serving Build and operate multi-model serving across modalities (text, voice, code, vision) on shared infrastructure Own the model lifecycle: download, deploy, serve, monitor, update, swap Drive inference optimization: latency, throughput, cost - including quantization, batching, caching, and routing strategies Ensure inference is fast and reliable for the agents and systems that depend on it Agentic Systems Architect and build the Agentic AI Platform - runtime infrastructure, orchestration systems, and developer tooling for autonomous agents Design multi-agent coordination systems enabling agents to collaborate and solve complex workflows Build robust tool-use infrastructure that allows agents to interact with APIs, databases, and services safely Implement workflow automation: agents that execute multi-step business and engineering tasks with appropriate guardrails Build safety and gu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are looking for an experienced PI MOL2 Manager to lead MOL2 process integration and drive process, yield, and product performance improvement. The candidate should have strong technical knowledge in semiconductor process integration, proven problem-solving and cross-functional leadership skills, and the ability to lead and develop a high-performing engineering team. Experience in technology transfer, yield improvement, defect reduction, and manufacturing execution is highly preferred. Meanwhile, have demonstrated ability to leverage AI tools to enhance productivity, data analysis, and problem-solving. Must be have (1) Cloud Assist (2) AI Supported (3) Agentic Solution ability. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To le

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: We are searching for an HBM IO Design Architecture Engineer. This role will focus on HBM IO / TSV IO design and analysis including electrical modeling, Signal Integrity (SI) and Power Integrity (PI) analysis, and design optimization across the HBM development cycle. The ideal candidate brings hands-on experience in design execution, simulation to silicon correlation, and cross-functional methodology development, and embraces AI-driven analysis and data-driven decision making to accelerate quality improvement cycles. Responsibilities will include, but are not limited to: High-speed IO design architecture for HBM products Define and standardize IO design quality process from architecture to silicon Define IO architecture, TSV IO performance targets, and design quality requirements for future HBM products. Develop IO and TSV modeling methodologies to support architecture tradeoff analysis, SI/PI evaluation, and design optimization. Drive simulation-to-silicon correlation and post-silicon learning feedback to improve design quality across HBM product generations. Leverage AI Assisted analytics to accelerate root cause identification from comp

About the job Turn product intent into the technical work that moves AI compute forward. As a Technical Product Owner, you will help component-based software teams deliver clear, prioritised and meaningful outcomes. You will connect product intent, engineering delivery and cross-team coordination. Your work will support software that spans bare metal silicon through to the machine learning tools stack. You will make complex systems easier to plan, explain and deliver. You will own component backlogs, shape roadmaps, refine epics and stories, and support sprint and PI planning. You will also surface dependencies, risks and trade-offs early. This role suits someone who brings calm, clarity and momentum to technical teams. You will help engineers focus on the work that matters most. The team and culture You will work with component-based software teams across Graphcore’s engineering organisation. These teams build across the full AI compute stack, from silicon-level software to ML tools. Work happens through clear planning, practical discussion and fast feedback. You will help teams visualise progress, involve the right people and make delivery risks visible early. Decisions are shaped by product outcomes, technical evidence and team insight. You will encourage open challenge, protect focus and enable empowered decision-making. What we’re looking for · Experience working as a Product Owner, or in a similar agile role. · Strong backlog management, refinement and roadmap development skills. · Ability to communicate clearly with technical and non-technical stakeholders. · Confidence working with technical teams, complex systems and cross-team dependencies. · Strong facilitation skills, with the ability to guide discussions to clear outcomes. · Strategic mindset, with empathy and the ability to bring calm, clarity and support. While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we e

About the job Shape the power-delivery architecture behind Graphcore’s high-performance AI compute systems, from voltage regulation through package, PCB and silicon. As Staff Power Integrity Engineer, you will provide technical leadership on Graphcore’s most complex power-delivery challenges. Your analysis and judgement will directly influence architecture and product decisions. You will define modelling strategies, optimise decoupling and analyse PDN impedance, voltage droop, transient response and regulator interactions. You will turn complex results into clear engineering decisions, requirements and sign-off approaches. You will lead significant PI issues through resolution and create alignment across silicon, package, board, power, systems and validation teams. You will also develop reusable methods and mentor engineers, raising power-integrity capability across Graphcore. The team and culture The Signal and Power Integrity team sits at the centre of Graphcore’s hardware development. We work across disciplines to understand electrical behaviour and guide consequential architecture decisions. You will own complex PI problems and drive them through to resolution. Decisions are grounded in modelling, first-principles reasoning, hardware evidence and clear assessment of uncertainty. You will challenge assumptions, communicate risk clearly and help teams make pragmatic trade-offs. Technical influence matters more than reporting lines. What we’re looking for Deep practical expertise in power integrity and complex power-delivery network design. Strong understanding of PDN impedance, transient behaviour, voltage droop, resonance, stability and decoupling across high-current digital systems. Ability to reason across silicon, package, PCB, voltage regulation and system boundaries. Strong capability in electromagnetic modelling, circuit simulation, model extraction and selecting appropriate abstraction methods. Engineering judgement to assess model validity, uncertainty an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview Micron’s Process Integration (PI) team is at the forefront of technology development and manufacturing excellence. The team focuses on optimizing semiconductor processes to improve yield, reduce costs, and enable next-generation memory devices. By collaborating closely with Technology Development, Product Engineering, Manufacturing, and Quality teams, Process Integration ensures seamless technology transfer while driving continuous improvement in product performance, quality, and reliability. Position Overview As a Process Integration Engineer, you will contribute to the development, optimization, and transfer of advanced semiconductor manufacturing processes for next-generation memory technologies. In this role, you will analyze process performance, drive yield improvements, and support qualifications of new technologies, materials, and equipment. You will work in a collaborative, fast-paced environment partnering with multi-functional teams to deliver industry-leading quality, reliability, and manufacturing excellence. Responsibilities Own semiconductor process modules and lead root cause investigations and failure analysis in time-sensitive manufacturing environments! Drive improvements in yield, cost efficiency, quality, and overall process performance. <

About the job Shape the power delivery that will make Graphcore’s next-generation AI compute systems reliable. As a Power Integrity Engineer, you will analyse power-delivery networks across silicon, package and PCB, turning complex behaviour into practical design recommendations. You will build PDN models, investigate parasitics, and use frequency-domain and time-domain analysis to understand stability, droop, resonances and transient response. Your work will directly inform decoupling, layout, and power and ground distribution choices. You will use electromagnetic simulation to understand resistance, inductance, coupling and impedance. You will also validate assumptions, identify technical risks, and connect simulation results with hardware measurements. You will start with clearly scoped PI problems, supported by experienced engineers when wider decisions are involved. As your capability grows, you will own larger parts of the PDN. The team and culture You will work alongside experienced PI engineers and colleagues across hardware disciplines, connecting analysis with real design decisions and measurements. You will own defined technical problems and move quickly from modelling to recommendations. Decisions are grounded in evidence, physical understanding and clear communication of uncertainty. You will contribute to design reviews, speak up when results expose risk, and take responsibility for the quality of your analysis. What we’re looking for Build, integrate and analyse PDN models for defined power rails, package structures, PCB designs or subsystems. Use frequency-domain impedance analysis and time-domain simulation to investigate voltage stability, droop, resonances and transient response. Evaluate decoupling choices and placement, considering capacitance, parasitics and the interaction between silicon, package and PCB. Use electromagnetic simulation to extract and understand resistance, inductance, coupling and impedance in power and ground structures. Che

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Process Integration (PI) team is at the forefront of technology development and manufacturing excellence. We focus on optimizing semiconductor processes to improve yield, reduce costs, and enable next-generation memory devices. By collaborating with cross-functional teams—including Technology Development, Product Engineering, and Manufacturing—the PI team ensures seamless technology transfer and drives continuous improvement in quality and reliability. Join our dynamic Process Integration team and contribute to the development and optimization of advanced semiconductor processes. This entry-level role offers hands-on experience in yield improvement, cost reduction, and technology transfer for next-generation devices. You will work in a fast-paced environment, collaborating with cross-functional teams to ensure best-in-class quality and performance. Responsibilities Act as a module owner to conduct root cause investigations and failure analysis in time-sensitive environments. Drive improvements in yield, cost efficiency, and quality. Run Design of Experiments (DOE) to enhance process capability and margin. Monitor trends and sustain line stability. Address top detractors to improve device yield and reliability. Lead workshops during technology transfer for next-generation devices. Start up, develop, and optimize processes for product quality and reliability.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. FY27 PI ENGINEER (Process Integration Engineer) Shape the Future of Semiconductor Innovation Are you passionate about semiconductor technology, process innovation, and solving complex manufacturing challenges? At Micron Technology, Process Integration (PI) Engineers play a critical role in bridging technology development and high-volume manufacturing. We are looking for talented engineers who are eager to drive process excellence, enable next-generation memory products, and leverage AI-driven </span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of the Heterogeneous Integration Group within Technology and Products, where we build High Bandwidth Memory solutions that power AI and ML platforms. Our team works at the edge of what’s possible, stacking and integrating advanced silicon technologies to deliver industry‑leading bandwidth, density, and power efficiency. We move fast, solve hard problems, and set technical direction others follow! This role sits at the center of next‑generation HBM development. As a senior SI/PI technical authority, you will shape system‑level decisions that directly impact performance, reliability, and scalability across multiple product generations. If you enjoy deep technical ownership, complex problem solving, and influencing architecture from concept to sign‑off, this role offers both challenge and impact. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Lead signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency‑ and time‑domain evaluation Define and drive power delivery architecture, impedance targets, and transient analysis Perform electromagnetic extraction and modeling across PCB, package, and interposer designs Establish SI/PI standards, methodologies, and sign‑off criteria for HBM system designs Provide clear technical direction in ambiguous or incomplete design environments Minimum Qualifications: 7 years of experience in

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: Expertly lead the NPI BP team, facilitating collaboration among representatives from ADT, HVM, Manufacturing, and PI. Ensure all Global BP processes are strictly implemented and all evidence is meticulously recorded, highlighting and mitigating risks. Assess provided evidence to determine if it meets BP requirements. Coordinate the accurate signing off and recording of transfer documents. Own NPI BP benchmarks, preparing 4-UP if benchmarks fall below targets. Adjust NPI plans in Fab based on product introduction schedules and Qual progress. Collaborate with NPI BP owners to improve current BP and deploy BP in Fab16. Represent NPI BP in audits and support sample shipments for customers, internal qualifications, and engineering. Understand product quality requirements and demand through communication with PEP. Manage CMOS corner samples, following corner BP due to longer cycle times. Attend PDT meetings to update NPI progress and engage in initial NPI planning through Network build meetings. Develop yield curves for each NPI DID, l everaging AI to build models. Minimum Qualifications: Bachelor’s degree in Engineering or a related area, or equivalent practical experience. Proven experience in NPI BP and technology development. Strong leadership and collaboration skills. Ability to assess and mitigate risks effectively. Excellent communication an

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an PDE Yield Enhancement (YE) Engineer within Package Development Engineering (PDE), you will be responsible for yield monitoring, excursion management, and yield stabilization during High Bandwidth Memory (HBM) New Product Introduction (NPI) . This role is critical to ensuring robust yield performance from first silicon through NPI ramp and early HVM , working closely with Process Integration (PI), MRDA, Process Engineering (PE), Assembly/Test Manufacturing, and Quality teams. You will act as a hands‑on yield owner during NPI builds, driving fast learning cycles, early risk detection, and disciplined yield recovery. Job Responsibilities: Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness,exercising sound judgment and complying with organizational standards and legal requirements. Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabled enhancements within one’s scope of work. Yield Loss Accounted For Account for HBM NPI builds across Post Wafer Finishing (PWF), Assembly, and

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. The PDE Process Integration (PI) Engineer is responsible for driving process integration excellence for High Bandwidth (HBM) products during New Product Introduction (NPI) . This role ensures robust process readiness, yield ramp, and cross‑module integration across Post Wafer Finishing PWF, assembly, and test , enabling successful execution of HBM technology roadmaps. The PI Engineer works cross‑functionally with Fab, Assembly, Test, Yield, Quality, and central engineering teams to identify risks early, resolve complex integration issues, and deliver NPI milestones on time. Job Responsibilities Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements. Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabled enhancements within one’s scope of work. NPI Execution & Support Execute assigned HBM NPI PI tasks following defined procedures and phase‑gate requirements Support NPI builds through lot tracking, data collection, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Responsibilities Yield Loss Accounted For Account for HBM NPI builds across PWF, Assembly, and test through defect breakdown and PFA submission to understand fail mode Work closely with PI to identify defect that is coming from their area to brainstorm for CIP Learn NPI processes, phase gates, and yield best practices Assist in maintaining yield dashboards and trackers. Support PI/PE/RDA in identifying and transforming processing data to account/ breakdown a yield loss Yield Deviation Control Analyze and report on yield deviation issue and trigger action from PI, PE or RDA Support block run and partial conversion build yield analysis to early detect any impact on yield Work closely with PCS team to identify SPC or FDC charts to put into YLR dashboard for shift left monitoring Yield Improvement Opportunities Brainstorm with staff from other departments to brainstorm for improvement opportunities to propose to PI Utilize software tool like Auto-diagnostics to find yield improvement opportunities Integrating Artificial Intelligence Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgement and complying with organizational standards and legal requirements Contributes to a culture of continuous improvement by identifying, testing, and sha