Principal Data Architect Jobs

Toast creates technology to help restaurants and local businesses succeed in a digital world, helping business owners operate, increase sales, engage customers, and keep employees happy. At Toast, Talent Acquisition runs on its tools. Greenhouse, GoodTime, and BrightHire are where every requisition, interview, and hiring decision actually happens — and no single person owns them end-to-end today. That is this role. As a Principal TA Systems Architect, you will be the technical owner of the TA tech stack: the person who configures it, integrates it, secures it, measures it, and decides where it goes next. You will partner closely with the TA Operations who live in these systems every day, with the broader People Systems and People Analytics teams who own the HRIS and downstream data, and with IT, Security, Legal, and Procurement on access, privacy, and purchasing. You will own the vendor relationships — roadmap conversations, renewals, escalations — and hold our partners to a standard. This is an individual contributor role today with a clear path to building and leading a small team as the function scales. If you want to own a domain, be the deepest expert in the building on it, and eventually hire people to extend it, this is that job. A day in the life (Responsibilities) Own the stack: Serve as system owner and top-tier administrator for Greenhouse, GoodTime, and BrightHire — configuration, permissions, workflows, approval chains, compliance settings, and release management. Own the integration layer between TA systems and the rest of the People stack: HRIS, background check, assessments, sourcing, and offer tooling, including API-based integrations and middleware. Run intake-to-resolution on system issues: triage, root-cause, fix, and close the loop with whoever reported it. Hold the change management discipline the stack needs — sandbox testing, documented configuration decisions, release notes, and user communications. Partner across the People org

Aliases: Principal Engineer, Senior Principal Engineer, Technical Architect, Principal Architect, Enterprise Architect (Engineering), Senior Technical Architect, Distinguished Engineer or Chief Architect at a smaller company About Truveta Truveta is the world's first health provider-led data platform with a vision of Saving Lives with Data. Our mission is to enable researchers to find cures faster, empower every clinician to be an expert, and help families make the most informed decisions about their care. Achieving Truveta's ambitious vision requires an incredible team of talented and inspired people with a unique combination of health, software, and big data expertise who share our company values. This opportunity Join the founding team of the Truveta India Development Center and play a pivotal role in shaping its future. As one of the early members, you will help build and scale a high-impact organization while contributing to the products and platforms that advance healthcare through data and AI. This is an unusual chance to influence both the technical direction and the culture of a growing global engineering hub. The Data Platform group in India owns parts of the pipeline that ingests, processes, stores, and serves healthcare data at a scale very few organizations operate at. Patients, doctors, and medical researchers deserve the same engineering rigor that has transformed other industries, and that is the work: correctness under volume, reliability under failure, and speed without cutting the corners that regulated health data does not allow anyone to cut. What you will do Define architecture across ingestion, processing, storage, serving, governance, and observability for the India-owned parts of the platform, aligned with Seattle. Set multi-platform technical strategy along with the sequencing that makes it achievable rather than aspirational. Remain hands-on where it counts: critical designs, prototyp

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About Our Team The AI Security team is a newly established organization within Micron's Cyber Defense & Resilience (CDR) group, reporting directly to the Deputy CSO. We provide AI and automation engineering expertise across CDR's security functions, partnering with Security Operations, Governance Risk & Compliance, Third-Party Risk, Security Awareness, and Security Architecture teams to strengthen the security of a global environment supporting 50,000+ employees and 100,000+ devices! Position Overview We are seeking a Principal AI Security Architect to serve as the senior-most technical authority for AI security within Cyber Defense & Resilience! This role will define and drive AI security strategy, be responsible for AI threat modeling and governance, lead AI-related incident response efforts, and act as the primary advisor to executive leadership on the secure use, defense, and response to emerging AI technologies and threats. Responsibilities Develop and own the AI security strategy, threat model, and roadmap for Cyber Defense & Resilience. Establish quarterly priorities for AI security initiatives and provide strategic direction across multiple security functions. Define risk classification criteria and review high-risk AI agent architectures, including systems with customer data access, autonomous decision-making, and external system integrations. Act as the lead coordinator for AI-related cybersecurity incidents, partnering with ent

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years or MSEE with 5+ years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years, or MSEE with 5+ years of releva

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. Company Overview We are building the next generation of cloud security infrastructure, focusing on advanced Data Exfiltration Protection (DXP) and unified Data Movement Policies (DMP). Our mission is to provide seamless, context-aware security that protects sensitive data without hindering developer velocity. We are looking for a visionary Principal Engineer to lead the technical strategy and architecture for our Data Movement and Perimeter control systems. Role Summary As a Principal Engineer in the Data Protection group, you will be the technical lead for the Data Exfiltration Protection (DXP) and Data Movement Policy (DMP) initiatives. You will bridge the gap between high-level security policy and low-level system enforcement, ensuring that our perimeter controls are robust, scalable, and deeply integrated with context-aware access policy frameworks. You will be responsible for the architectural evolution of our egress control systems, moving from simple IP-based rules to sophisticated, content-aware, and identity-driven data movement governance. AS A PRINCIPAL SOFTWARE ENGINEER - IDENTITY, DATA SECURITY AND TRUST AT SNOWFLAKE YOU WILL: Architectural Leadership: Lead the design and implementation of the Data Movement Policy (DMP) framework, ensuring it can handle complex

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has advanced the world’s most innovative memory and semiconductor technologies. As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next‑generation high‑bandwidth memory products. You will evaluate block‑level and full‑chip functionality, solve complex challenges in building, and collaborate with a distributed team to deliver highly reliable, industry‑leading HBM solutions. This role provides the opportunity to contribute to groundbreaking DRAM design, TSV‑based 3D integration, and high‑speed mixed‑signal architectures supporting Machine Learning and AI applications. Responsibilities Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Member of Technical Staff HBM Design Architect, you will be responsible for design and development of high-speed interface between DRAM and Base die in HBM cube! This includes designing the DRAM command and control logic, as well serializing and de-serializing scheme. You will collaborate with a highly creative and motivated development team applying brand-new memory technologies to build groundbreaking HBM products! Responsibilities: Responsible for the high-speed DRAM and Base die interface in HBM cube. Design the DRAM command and control logic, as well as serializing and de-serializing scheme at the interface. Conduct circuit simulations using standard industry simulators such as FINESIM, HSPICE and VERILOG Collaborate with data path design on floor planning and full chip testbench. Analyze timing/area/power in high-speed DRAM or mixed-signal design. Contribute to the development of new HBM product opportunities by assisting with the overall design, layout, and optimization of Memory, Logic, and Analog circuits. Qualifications: Extensive experience with DRAM operation and JEDEC specifications across DDR, LPDDR, GDDR, and HBM product families. Strong technical expertise in analog and mixed-signal circuit design. Hands-on proficiency in DRAM command decoding, bank logic, and RAS/CAS chain design. Demonstrated innovation and problem‑solving capabilities in

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 200+ public data centers globally and thousands of private sites at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. Role We are looking for an Architect / Senior Principal Software Development Engineer (Layer 7 Security & Proxy) to join our team. This is a hybrid role (minimum 3 days a week in Santa Clara, CA office), reporting to the Director, Software Development Engineering in the Zero Trust Exchange department. This architect role is essential to provide technical leadership for the ZIA proxy architecture, with a strong focus on advanced Layer 7 protocols and SSL inspection. You will help improve the quality of code shipped to production by driving sound architectural decisions, implementing innovative solutions, and raising the overall engineering bar for the team. Additionally, you will play a key role in modernizing the ZIA code base by addressing technical debt, fixing existing issues, and rewriting components where necessary. Ultimately, this role is critical for supporting and accelerating the delivery of key proxy roadmap

NVIDIA builds the silicon behind AI, accelerated computing, and graphics. Every watt of performance and every degree of thermal headroom traces back to decisions made in power, performance, and thermal architecture. We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas. We start with initial concepts and advance to product differentiation across NVIDIA's roadmap. We are hiring a Principal System Power Management and Performance Architect who operates at the ambiguous boundary where workload behavior, silicon capabilities, firmware policies, and platform constraints collide, and who turns that ambiguity into architecture that survives across multiple silicon generations. SCG scope spans architecture, design, software, operations, platforms, and productization. This role shapes system, platform, and data center features and behavior, and partners with teams across NVIDIA. What You'll Be Doing: The work here is rarely well-defined when it arrives. You will be given problems that appear to be performance gaps or power anomalies and encouraged to build a framework for solving them, not just tackle a single instance. Define the multi-generation roadmap for system-level power and performance features, grounded in prototyping, use-case analysis, and cost/benefit trade-offs across segments. You will decide what problems are worth solving and why. Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features. Your decisions improve product performance, power, and reliability across product lines — not just the current program. Lead system-level boot and IST architecture defining how power and clock domains initialize, sequence, and recover across complex multi-IP systems where the interaction space is large and the failure modes matter. Drive power management strategy at data

For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day. Observability Engineering owns the breadth and depth of observability and telemetry at Smartsheet. We build and operate the shared platform every engineering team depends on to understand how their software behaves in production (metrics, logs, distributed traces, RUM, synthetics, and AI/agentic telemetry) across a global, multi-region, commercial and government footprint. We are consolidating ownership of all of it into a single correlated platform, and treating telemetry as what it actually is: one of the largest and most valuable datasets at the company. It's a broad mandate with real scope to shape, and we hold this internal platform to the same rigor, reliability, and product standards as customer-facing software. As a Principal Software Engineer (Observability & Telemetry Data) , you will set the technical direction for how Smartsheet collects, models, stores, and derives value from telemetry data. This is an architect role: you will define the telemetry data platform and the standards that govern it, carry that architecture across engineering org boundaries, partner with our Data and AI Platform teams on Databricks and MLflow integration, and act as the company's definitive technical voice on observability. You will influence roadmaps you do not own, resolve the hard design trade-offs between fidelity and cost, and raise the technical bar for every engineer instrumenting a service. This full-time position reports to the Team Lead, Observability Engineering and can be located in our Bellevue, WA off

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: Develop system-level solutions, tools, and methodologies to optimize DRAM performance, power efficiency, and cost. Collaborate with multi-functional teams to ideate, evaluate, and implement innovative DRAM and memory system solutions. Analyze system behavior and assess solution effectiveness, making data-driven optimizations and trade-offs. Drive architectural innovation for current and future generations of DRAM technologies. Communicate complex technical concepts clearly and mentor team members through training and technical guidance. Using AI in applicable job functions Minimum Qualifications: Proven experience in memory design and product engineering, memory specifications and operations, or memory system architecture and usage. Minimum of 7 years of experience in the memory or semiconductor industry. Strong understanding of DRAM architectures and system-level interactions. Ability to analyze complex technical problems and drive solutions. Bachelor’s degree in Electrical Engineering, Physics, Computer Engineering, or a related field, or equivalent experience. Preferred Qualifications: Experience with advanced memory technologies such as LPDDR5/6, DDR5/6, GDDR6/7, or HBM3E/4. Strong analytical and problem-solving skills with a passion for innovation. Ability to identify complex technical challenges and develop creative, scalable solutions. Deep under

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. We are hiring a Principal Engineer II to architect the core data processing engine of the Snowflake Data & AI Cloud. At Snowflake, we believe that high-performance, unified compute fabrics are the indispensable building blocks for Agentic AI. Autonomous agents require more than just models; they require a high-fidelity, low-latency state layer to reason, act, and persist context. This role is not about building traditional data processing pipelines or legacy ETL/ELT workflows; it is about building the core distributed systems and atomic primitives that make those agentic workflows possible. In this role, you will be a lead architect of the Snowflake Data Transformation Engine. You will design and implement the fundamental transformations infrastructure—Stateful Stream Processing Engines, Incremental View Maintenance Engine, Materialization Internals, and the Distributed Orchestration Fabric. Our solid foundation supporting the seamless transition for enterprises between batch and streaming through Dynamic Tables, Streams & Tasks, and DBT Projects is the starting point. Your architectural work will extend the reach of the core engine to accelerate and support the massive scale of the Snowpark and Spark ecosystems. You are building the systems that allow both data eng

This is where your work makes a difference. At Baxter, we believe every person—regardless of who they are or where they are from—deserves a chance to live a healthy life. It was our founding belief in 1931 and continues to be our guiding principle. We are redefining healthcare delivery to make a greater impact today, tomorrow, and beyond. Our Baxter colleagues are united by our Mission to Save and Sustain Lives. Together, our community is driven by a culture of courage, trust, and collaboration. Every individual is empowered to take ownership and make a meaningful impact. We strive for efficient and effective operations, and we hold each other accountable for delivering exceptional results. Here, you will find more than just a job—you will find purpose and pride. Job Summary Designs and delivers scalable software solutions, applying strong engineering practices and technical judgment. Plans and executes defined projects with minimal guidance while collaborating across functions. What you’ll be doing Plan and deliver defined software projects, including schedules, dependencies, and coordination with development and support teams. Design, architect, develop, test, and maintain scalable .NET applications, APIs, and microservices. Design and implement integrations using REST APIs, WebSockets, SignalR, and real-time voice communication technologies. Apply HIPAA-aligned security practices for data handling, authentication, voice communications, messaging, and notifications. Develop clean, maintainable code and dri