Senior Business Planning Analyst Jobs

NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. NVIDIA is looking for phenomenal people like you to help us accelerate the next wave of artificial intelligence. We are looking for a highly motivated senior software engineer for an exciting role in our communication libraries and network software team. The position will be part of a fast-paced crew that develops and maintains software for complex heterogeneous computing systems that power disruptive products in High Performance Computing and Deep Learning. What you will be doing: Design, implement and maintain highly-optimized communication runtimes for Deep Learning frameworks (e.g. NCCL for TensorFlow/Pytorch) and HPC programming interfaces (e.g. UCX for MPI/OpenSHMEM) on GPU clusters. Participating in and contributing to parallel programming interface specifications like MPI/OpenSHMEM. Design, implement and maintain system software that enables interactions among GPUs and interactions between GPUs and other system components. Creating proof-of-concepts to evaluate and motivate extensions in programming models, new designs in runtimes and new features in hardware. What we need to see: M.S./Ph.D. degree in CS/CE or equivalent experience. 5+ years of relevant experience. Excellent C/C++ programming and debugging skills. Strong experience with Linux. Expert understanding of computer syst

NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. We are looking for a motivated Performance engineer to influence the roadmap of our communication libraries. The DL and HPC applications of today have a huge compute demand and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! This is an outstanding opportunity for someone with HPC and performance background to advance the state of the art in this space. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Conduct in-depth performance characterization and analysis on large multi-GPU and multi-node clusters. Study the interaction of our libraries with all HW (GPU, CPU, Networking) and SW components in the stack Evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available Triage and root-cause performance issues reported by our customers Collect a lot of performance data; build tools and infrastructure to visualize and analyze the information <li

The NVIDIA DGXC Data Services team builds cloud-native systems, frameworks, and services for managing data across hybrid and multi-cloud infrastructure. We are building the next-generation data and storage infrastructure to solve some of the hardest problems in AI: storage, access, ingestion, governance, observability, and data management for exabyte-scale, high-performance GPU-based training and inference jobs. Our work gives NVIDIA teams the foundational capabilities they need to build, train, deploy, and operate AI products at scale without reinventing critical data infrastructure for every workload. What you will be doing: Build storage technologies, client libraries, and filesystem frameworks that help AI workloads access data across object stores, file systems, and hybrid cloud infrastructure. Develop high-performance storage paths for training and inference workflows, including data loading, checkpointing, caching, POSIX-style access, and object-store integration. Build observability systems that diagnose storage bottlenecks, attribute GPU idle time to I/O behavior, and expose actionable telemetry through production monitoring stacks. Improve performance, scalability, and reliability of storage systems serving massive datasets, deep directory trees, and high-concurrency AI workloads. Work closely with internal AI teams, platform teams, SRE, and operations to validate storage behavior against real workloads and production environments. Use modern software engineering practices, including AI-assisted and agentic development workflows, while maintaining high standards for design, testing, security, performance, and verification. What we need to see: BS in Computer Science, Information Sys

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior/Staff Engineer in CPQE Deviation Management at Micron Technology, Inc., you will have a meaningful role in advancing quality excellence throughout Micron’s global Frontend manufacturing network. The mission of the Central QE organization is to raise Micron’s quality standards through focused collaboration with manufacturing sites, Global Quality teams, and Central partners. Join our driven team and contribute to the pursuit of flawless quality management! Key Responsibilities Lead global quality initiatives to build, implement, and sustain robust deviation management processes and systems. Drive the Issue Tracker SWAT team, deploying Best-Known Methods (BKMs) and standardizing practices across manufacturing sites. Analyze and resolve minor deviations (e.g., yield spread, yield deviation & minor GPSS) by providing data-driven recommendations to improve fab performance. Drive quality improvement efforts, resolving non-conformances and introducing corrective and preventive steps. Continuously improve quality metrics such as $CoNC and %NCD through innovative solutions and system improvements. Form and lead cross-functional task forces to address quality health concerns and improve metric performance across sites. Drive innovative, AI-powered project solutions to optimize efficiency, accelerate problem resolution, and deliver sustained benchmark performance. Set up key Quality program from planning stage and well verse with deployment and proliferation strategy in the

Our Purpose Mastercard powers economies and empowers people in 200&#43; countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title and Summary Senior AI Engineer, Big Data & AI Solutions Overview The Security Solutions Data Science team develops AI and machine learning capabilities that help protect the global payments ecosystem from fraud and cyber threats. Supporting Mastercard’s Safety Net product, the team develops and enhances models that analyze billions of transactions and identify suspicious activity. As a Senior AI Engineer, you will work at the intersection of big data engineering and AI/ML, helping build and support the data, features, models, and production processes behind fraud detection. Ideal Candidate Profile You are a big data and AI/ML engineer who has used Apache Spark in a professional environment and has hands-on experience working within CI/CD-driven engineering environments. You understand how large-scale data moves from raw inputs through data and feature pipelines into machine learning models, and how those models are deployed, monitored, and improved in production. Large-scale data → Spark/PySpark → Data & Feature Pipelines → ML models → Production Deployment→ CI/CD→Monitoring & Drift Detection → Optimization & Retraining Experience with Generative AI, RAG, LLMs, or agentic AI is valuable, but the foundation for this role is large-scale data engineering and production AI/M

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for a Senior Software Performance Engineer for Autonomous Vehicles! Our team builds NVIDIA’s end-to-end autonomous driving applications. We are seeking senior software engineers who are passionate about performance with an interest in optimizing self-driving solutions that run on NVIDIA’s multi-computer and heterogenous HW architectures. What you’ll be doing: Develop, maintain and optimize latency and throughput of NVIDIA’s L2/L3/L4 autonomous driving solutions. Devise acceleration strategies and patterns to improve software architecture and its efficiency on our computers with multiple heterogeneous hardware engines while meeting or exceeding product goals. Develop highly efficient product code in C&#43;&#43;, making use of algorithmic parallelism offered by GPGPU programming (CUDA)/ARM NEON while following quality and safety standards such as defined by MISRA. Collaborate with HW, product, OS, and safety teams to design next-gen products. What we need to see: MS or PhD degree in Computer Science, Computer Architecture, Electrical Engineering or related field (or equivalent experience). 12&#43; years of relevant professional experience. Excel

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI,

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding opportunity to join a world-class team and make a significant impact in the semiconductor industry! What You'll Be Doing: Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms. Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST, memory BIST, and scan compression. Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology. Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre-silicon through production deployment. Develop and standardize methodologies, processes, and workflows for silicon bring-up, crafting reusable checklists and playbooks. Improve cross-team communication, work, and handoffs. Guide and mentor junior engineers, helping them navigate complex build trade-offs to achieve world-class quality and efficiency. What We Need To See: BSEE (or equivalent experience) with 5&#43; years, MSEE with 3&#43; years, or PhD in DFT or related domains. Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation. Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate builds using vendor tools. Experience in silicon debug and bring-up with an understanding of pattern formats, failure processing, and test program development. Strong programming and scripting skills. Excellent written and or

This is where your work makes a difference. At Baxter, we believe every person—regardless of who they are or where they are from—deserves a chance to live a healthy life. It was our founding belief in 1931 and continues to be our guiding principle. We are redefining healthcare delivery to make a greater impact today, tomorrow, and beyond. Our Baxter colleagues are united by our Mission to Save and Sustain Lives. Together, our community is driven by a culture of courage, trust, and collaboration. Every individual is empowered to take ownership and make a meaningful impact. We strive for efficient and effective operations, and we hold each other accountable for delivering exceptional results. Here, you will find more than just a job—you will find purpose and pride. RESUME Le.a Senior Specialist, Medical Information sera responsable de la gestion de tous les aspects support de l’information médicale pour tous les produits Baxter pour les clients internes et externes en France & Benelux, avec un support ad-hoc pour la région EMEA au sens large. Il/elle facilite le développement et la mise en œuvre opérationnelle de la stratégie d'Information Médicale dans la région EMEA et plus particulièrement dans la région France & Benelux. TACHES ET RESPONSABILITES PRINCIPALES • Apporter un service d'informations médicales de qualité réactif et non sollicité aux clients internes et externes, en enregistrant des détails complets dans le système de gestion des appels d’informations médicales et assurer la responsabilité de la maintenance du système. • Offrir une formation aux équipes internes et externes susc

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. Help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 12&#43;, MSEE with 10&#43;, or PhD with 6&#43; years of experience in DFT design & power

As a member of the Hardware Infrastructure EDA Compute team, you will optimize, scale, and support workload scheduling systems that directly impact design velocity and infrastructure efficiency. Success in this role requires both operational precision along with developing and supporting forward-looking resource management solutions that address evolving compute demands. Beyond day-to-day operations, the role drives improvements in observability, service reliability, and automation, ensuring the EDA compute environment remains resilient, measurable, and aligned with long-term engineering demands. What you'll be doing: Manage, scale, and optimize job scheduling systems (LSF, Slurm, etc.) in a large-scale, multi-site environment supporting EDA and other compute-intensive workloads Analyze scheduler and infrastructure performance data to identify systemic bottlenecks and drive measurable improvements in utilization, throughput, and turnaround time Lead problem solving across scheduler, OS, and workload layers, ensuring timely resolution of service-impacting issues Identify recurring operational challenges and implement targeted automation or process improvements to reduce manual effort and prevent repeat incidents Help define and track reliable metrics and SLOs for service performance and reliability, partnering with customers to ensure expectations are realistic and measurable Contribute to operational standards, documentation, and best practices to improve consistency across sites Partner directly with customer teams to clarify requirements, translate technical tradeoffs, and drive issues to closure What we need to see: Bachelor’s degree in Computer Science or related field, or equivalent experience Minimum 5&#43; years of experience operating and supporting large-scale Linux-based

As a member of the HW Infrastructure Storage Strategy team, you will be the bridge between storage infrastructure and the chip design (e.g. NVIDIA GPUs and CPUs) workloads that depend on it. You will focus on going hands-on to understand how storage behavior impacts EDA (Electronic Design Automation) and HPC workload performance in general — and what to do about it. You’ll evaluate next-generation storage technologies, design POCs grounded in real workload profiles, uncover gaps in observability, and drive strategic decisions like data placement during datacenter transitions. This is a rare role where you’ll work at the intersection of storage systems and chip design workflows at a scale few companies reach — petabytes of active data, millions of files per job, and thousands of concurrent users. You’ll develop NVIDIA’s storage strategy and have a direct, measurable impact on engineering velocity. What you'll be doing: Lead storage technology evaluations — design and execute POCs for platforms such as NetApp, VAST, and others, using real EDA workload profiles to benchmark performance, metadata behavior, and compatibility Analyze how storage configurations and architecture choices impact EDA workload runtime in production, and recommend tuning or architectural changes to reduce job execution time Identify gaps in storage telemetry and observability — define what metrics are needed and how to correlate storage behavior with jobs running on the environment Support datacenter lifecycle programs — expansions, technology refreshes, and site exits — by mapping workload placement, identifying required data, and minimizing data replication scope Define storage policies and best practices — data lifecycle, tiering strategies, snapshot/clone workflows (e.g., FlexClone for EDA workspace branching), and capacity planning recommendations Collaborate with IT, EDA tool teams, EDA operations, and

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in the world—spanning 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs powering Autonomous Machines, Robotics, and Industrial systems. You will innovate at scale, designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that consistently delivers breakthrough performance across multiple high-impact tape-outs each year. What you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms. Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions. Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio. Guide and mentor junior engineers, helping them navigate complex design

NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule. Performing physical layout for silicon interposer using Cadence tools. Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance. Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists. Propose layout design trade-offs to the PTL for resolution and implementation. What we need to see: Hold a B.S. Electrical Engineering or equivalent experience Minimum of 5&#43; years proven experience in Mask and Layout Design. Deep understanding of layout concepts in submicron CMOS technologies. You are an authority with Cadence layout tools - particularly Virtuoso. Knowledge of Integrity auto-routing is a plus. Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc. Proficient in scripting languages like Perl, Python, S

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade. As a leader in the semiconductor industry, we build solutions that inspire and transform technology. With plans to invest more than $150 billion globally over the next decade in leading-edge manufacturing, we are looking for passionate people to join our Boise expansion team and contribute to the growth and innovation of the semiconductor industry. As a Senior Dry Etch Process Engineer you will be primarily responsible for starting up, developing, and optimizing processes to improve product quality, driving process yield improvements, cost reduction, productivity improvement and risk management as well as resolving manufacturing line problems. Your expertise will give to the production of high-quality semiconductor components that are pivotal to our customers' success. You will work closely with multi-functional teams to tackle process issues and implement solutions that improve efficiency and yield. Your passion for engineering and willingness to learn will help us overcome the challenges of this fast-paced industry. We are looking for someone who enjoys hands-on work, values collaboration, and is eager to dive deep into the technical aspects of semiconductor manufacturing. Responsibilities Strong process area knowledge DRAM development and manufacturing experience