Senior Design And Analysis Engineer Jobs

What you’ll do Own the tissue-class segmentation and labeling models for the ultrasound CT clinical analysis layer, and the pipelines that make them trainable and verifiable. Retune across 2D per-slice, 3D volumetric, and 2D×3D fusion as reconstructed image inputs are continuously updated, and clinical indications for use expand. Define training/evaluation pipelines, datasets, and metrics from the ground up or from open source; map model behavior to user needs and design requirements. Work with data labeling contractors, expert clinicians, and our internal cloud/data teams on labeling specs, QC, and dataset versioning. Help productionize models into a versioned, HIPAA-bound analysis service: reproducible/low-latency inference, per-prediction confidence, drift monitoring, and safe fallbacks. What we’re looking for Strong applied ML experience with a track record of developing new models — architecting, training, and evaluating from scratch as well as benchmarking against existing models. Experience with image segmentation (semantic/instance, 2D and ideally 3D/volumetric) and the modeling and training-data choices that make it robust across diverse patient anatomy. Comfortable moving fluidly between open-ended research iteration and producing quantifiable, testable models. Fluent in modern deep-learning tooling (e.g., PyTorch) and current development practices. Comfortable working under design controls, where model changes carry documentation and verification weight. Useful experience Image segmentation and label generation with modern architectures (U-Net / nnU-Net, 3D U-Net, transformer-based and promptable segmentation like SAM), including the geometry that ties voxel- and mesh-level predictions back to a coordinate frame. Learning under limited or noisy supervision: self-supervised / semi-supervised methods (masked autoencoders, contrastive pretraining like DINO/SimCLR), active learning, weak labels, and simulation-driven pretraining. Hands-on experience with data

For more than 30 years, SonicWall has delivered a partner-first unified cybersecurity portfolio that helps SMBs, MSPs, and IT teams consolidate network security, endpoint security, security service edge (SSE), and threat response across hybrid environments. By bringing connected technology, real-time threat intelligence, automation, and expert services together, SonicWall helps organizations simplify security operations, achieve better security outcomes, and lower total cost of ownership. Backed by a global ecosystem of more than 17,000 partners, SonicWall delivers enterprise-grade protection built for SMB and mid-market realities. For more information, visit www.sonicwall.com or follow us on X, LinkedIn , Facebook , and Instagram . We are seeking an experienced Hardware Design Engineer to lead the end-to-end development of next-generation network security appliances. This individual will be responsible for all phases of hardware product development, including requirements definition, architecture, detailed design, prototyping, validation, manufacturing support, and production release. The ideal candidate will have extensive experience designing high-performance networking platforms, embedded systems, and security-focused hardware products. Key Responsibilities Hardware Architecture & Product Development Own the complete hardware design lifecycle from concept through production and sustaining engineering. Translate product requirements into hardware architectures and detailed design specifications. Conduct technology evaluations, design trade-off analyses, and recommend optimal solutions. Select and qualify key components, technologies, and vendors. Drive product lifecycle management (PLM) activities, including product introduction, production release, field support, and post-launch analysis. Design & Development Design complex multi-layer PCBs for networking and security appliances. Perform circuit design, schematic capture, signal integ

Our Purpose Mastercard powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title and Summary Senior Software Engineer Job Overview: Responsible for the analysis, design, development, testing, and delivery of secure, scalable software solutions. Define requirements for new applications and customization adhering to Mastercard standards, processes, and best practices. Develop, customize, and test applications to integrate to Mastercard specifications. Provide leadership, mentoring, and technical training to other team members. Major Accountabilities • Plan, design, architect, and develop secure, scalable, and maintainable technical solutions and alternatives to meet business requirements in adherence with Mastercard standards, processes, and best practices • Lead day-to-day system development and maintenance activities of the team to meet service level agreements (SLAs) and create solutions with a high level of innovation, cost effectiveness, quality, reliability, and faster time to market. • Accountable for the full systems development life cycle including creating high-quality requirements documents, use cases, designs, and other technical artifacts including but not limited to detailed test strategies, performance benchmarking, release rollout and deployment plans, contingency/back-out plans, feasibility studies, cost and time analysis, and detailed estimates. • Design, develop, test, dep

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle. What you will be doing: Own end-to-end manufacturing test methodology across all test stages. Translate system specs and product POR into DFP requirements, test content, coverage, and flows. Define and maintain the DFP roadmap, including infrastructure and turning point planning. Partner multi-functionally to implement test content, debug hooks, and coverage improvements. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. Embed testability requirements into design to enable robust screening and debug. Define data and analytics frameworks to support yield analysis and continuous improvement. Lead DFP documentation as the single source of truth and feed findings into future methodologies. What we need to see: MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 6&#43; years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. <

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Our Senior Applied AI Engineer builds and operate production-grade AI systems that extract meaning from large-scale unstructured document collections, enabling enterprise data discovery classification, and governance. This role owns the full lifecycle of graph intelligence solutions — from problem definition and data modelling, to building and enriching knowledge graphs, and deploying ML- and LLM-assisted analytics in production. The focus is on semantic and contextual analysis of unstructured data to uncover relationships, patterns, and insights that support AI safety, security, and compliance requirements. WHAT YOU'LL DO Design, build, and deploy graph-based AI solutions, combining knowledge graphs , LLMs, and ML models applied to large-scale unstructured data Define and own data pipelines that extract, transform, and enrich entity relationships into production-grade knowledge graphs Integrate LLMs and ML models into text processing pipelines for classification, embedding generation, document similarity, and semantic analysis Design, deploy, and operate graph and vector databases to support retrieval, reasoning, and analytics Optimize models and inference pipelines for production constraints including latency, throughput, cost, and infrastructure Deploy, monitor, and iterate on ML systems in production environments ensuring reliability and continuous integration Drive architectural decisions and tech

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. We are looking for an Senior Engineer in Product Engineering, NAND Validation, specializing in functional and design validation of advanced NAND products . Experienced in silicon and simulation‑based validation, electrical failure analysis, and cross‑functional issue closure. Strong focus on automation, data‑driven validation, and applied AI/ML techniques to improve test efficiency, coverage, and debug productivity. Key Responsibilities & Achievements Designed and executed functional and design validation flows for advanced RG NAND devices using silicon and simulation platforms Developed deterministic usage‑case tests and random sequence generators to validate NAND commands and customer‑mode features Performed electrical failure analysis of issues seen, root‑cause investigations (including digital and analog circuitry), and drove issue resolution with cross-functional teams Implemented automation frameworks using C‑based programming, Python, and Perl to improve test development and execution efficiency Applied AI/ML‑assisted techniques (data analytics, patter

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon IP designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Good understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing experience is encouraged. Hands on experience in building SPICE testbenches at Block, Fullchip Level. Hands-on experience in building the COSIM/ Mixed signal verification environment is encouraged. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills us

The Quality Engineer will interact with Corporate Quality, Field Quality, Manufacturing, Design Engineering, and fleet operations to ensure the products released to service are meeting design specifications, functionality, customer expectations, and required documentation. The successful candidate must have the ability to meet tight deadlines, have strong interpersonal and communication skills, be detail-oriented, and be able to work independently. In this role, you will: Manage quality issue tracking to implement Containment, drive Root Cause Analysis and Corrective Action for non-conformances identified during production quality audits and vehicle release process. Support diagnosis of issues reported during Rider Quality Audit and EFR process ; establish standard inspection process and define required tools. Design, champion, and execute strategic continuous improvement initiatives to enhance the effectiveness and efficiency of production quality audit, EFR and issue resolution Work cross-functionally with Supplier Quality, Manufacturing and Vehicle Development to strategically resolve systemic product and process issues. Support develop and review of PFMEA and Control Plans to ensure compliance and robust risk mitigation strategies for all critical manufacturing processes. Good ability to communicate technical results clearly and accurately and drive issues to successful closure. Qualifications BS in Mechanical, Manufacturing, or Industrial Engineering Minimum 8 years of experience in a manufacturing environment, preferably automotive, aviation or contract manufacturing. Proven expertise in advanced problem-solving methodologies (e.g., Shainin Red X, Six Sigma Black/Green Belt) and demonstrated success driving systemic quality improvements across the value stream. Strong planning, organizational, analytical, negotiation, interpersonal, decision-making, oral

About Mixpanel Mixpanel is the leading product intelligence and analytics platform, trusted by more than 29,000 companies to help understand how people use the products they build. By combining powerful analytics with AI that knows your business, Mixpanel helps teams see what’s working, diagnose what’s not, and decide what to build next. Learn more at mixpanel.com . About the Team The Proactive Insights team is a newly formed team at the center of Mixpanel's AI-first analytics vision. With a greenfield charter, we're building the intelligent layer that transforms Mixpanel from a tool you query into a partner that works for you. We answer the question every data-driven team asks: "What changed, why, and what should I do about it?" We proactively keep users informed about what matters in their data, delivering the right insights and recommendations at the right time, to the right places, both inside and outside of Mixpanel. Some examples of what we are building: AI-powered root cause analysis : intelligent agents that diagnose why metrics changed, identify contributing factors, and recommend what to do next AI automations for KPI monitoring : always-on agents that track your key metrics and deliver insights to Slack, email, or directly in Mixpanel Intelligent alerts and anomaly detection : monitoring powered by models like TimesFM that surfaces meaningful shifts in your data About the Role As a Software Engineer on Proactive Insights, you'll build the features that transform how teams stay on top of their data. You'll work across the full stack, from React frontend experiences to Python backend services to integrating with our query engine, to ship workflows that surface insights users didn't know to ask for. You'll collaborate closely with Product and Design to shape what proactive analytics looks like, and with our AI Engine team to leverage shared infrastructure for orchestration, evaluation, and observability. This is a high-impact role on a small, fast-moving tea

We are now looking for a Senior CPU Performance Developer Technology Engineer. NVIDIA is seeking an outstanding computer scientist to join its Compute Developer Technology (Devtech) team. This role focuses on research and development techniques to optimize key Cloud and HPC CPU workloads on NVIDIA’s CPU. This includes performing in-depth analysis and optimization to ensure the best possible performance on the current and future generations of NVIDIA CPU. What you will be doing: Engage directly with the developer community and experts in their field to understand and address the problems they are solving today and tomorrow. Guide key framework and application developers, contribute directly to their software stack, libraries or develop reference code. Join efforts with diverse groups at NVIDIA such as architecture, research, libraries, tools, system software, and product management teams to constantly improve our products. Influence the design of NVIDIA next-generation architectures and software stack by investigating the impact on application performance and developer efficiency. What we need to see: A BS, MS, or PhD degree in computer science or equivalent experience, and 8&#43; years of relevant experience. Strong knowledge of C/C&#43;&#43; and/or Fortran with solid understanding in software design, programming techniques, and algorithms. Hands-on experience with benchmarking and optimizing enterprise and cloud workloads. Good communication and organization skills, with a logical approach to problem solving, good time management, and task prioritization skills. NVIDIA is at the forefront of breakthroughs in Artificial Intelligence, High-Performance Computing, and Visualization. Our teams are composed of driven, innovative professionals dedicated to pushing the boundar

Job Details: Job Description: The Role and Impact You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As a senior IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will technically lead teams in developing verification plans, creating test benches, and building environments to thoroughly validate meaningful parts of the chip — complex IPs and subsystems. Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more. Business group You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products. The group produces innovative technologies and solutions for hyperscalers, cloud providers, networking, AI and other specialized workloads. </spa

NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth! We are the Silicon Power Team within the Silicon Co-Design Group. We architect and deliver groundbreaking solutions for productizing NVIDIA's chips across consumer, professional, server, embedded, mobile, and automotive markets. Silicon characterization, correlation to arch and design expectations, product spec finalization, and productization techniques and infrastructure are our day-to-day work — always on the bleeding edge of the industry. Small decisions here have outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product delivers in the field. We are hiring a Senior Silicon Power Engineer to own power-feature productization on a flagship silicon program. This is not a coordination role, and it is not a compliance role — it is the seat where power features either work at scale or become the reason a program slips. The two highest-leverage problems in this seat: Close the hardest multi-functional power failures before they gate a program. Take ambiguous, cross-boundary issues across architecture, firmware, validation, and platform to root-cause closure — with productized fixes and reusable methodology the next program can inherit. Build AI-enabled characterization as a real capability, not a demo. Every bring-up generates terabytes of characterization, shmoo, and telemetry data. Deploy AI workflows for data analysis, metric extraction, trend detection, and cross-bring-up correlation — with the guardrails and validation discipline to make them trustworthy enough to gate production decisions! <

At Rockstar Games, we create world-class entertainment experiences. Become part of a team working on some of the most rewarding, large-scale creative projects to be found in any entertainment medium - all within an inclusive, highly-motivated environment where you can learn and collaborate with some of the most talented people in the industry. Rockstar is on the lookout for a passionate Senior Security Platform Engineer who is skilled at diving into complex software designs to identify security flaws and vulnerabilities. This is a full-time, in-office position based out of Rockstar’s NYC headquarters in Downtown Manhattan. WHAT WE DO The Rockstar Games Application Security team partners with numerous development teams across the company to incorporate security practices throughout the software development lifecycle. We strive to understand the threat landscape affecting our development studios, the gaming industry, and the world at large to define secure development standards and guidelines to safeguard our business and protect our players. We independently assess our application code and builds through various techniques (static analysis, dynamic analysis, software composition analysis, etc.) to identify potential vulnerabilities and design flaws and work with development teams to remediate. RESPONSIBILITIES Architect and support secure software development lifecycle operations embedded in software development pipelines. Provide technical security guidance to developers, team leads, and producers. Drive remediation efforts behind internally and publicly identified vulnerabilities. REQUIREMENTS 5+ years of experience working in a professional, academic or research environment identifying and remediating security bugs/flaws, assisted by automated pipelines. Knowledge of common web security vulnerabilities (e.g., OWASP Top 10), client-side security landscape, attack techniques and remediation tactics/strategies. Experience implementing and tuning SAST, SCA

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. In this role, you will: Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. Design mechanisms for routing, arbitration, ordering, flow con

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary: We are looking for an Engineer/Senior Engineer in Product Engineering, NAND Validation/Characterization , specializing in functional and design validation/Characterization of advanced NAND products . Experienced in silicon and simulation‑based validation, electrical failure analysis, and cross‑functional issue closure. Strong focus on automation, data‑driven validation, and applied AI/ML techniques to improve test efficiency, coverage, and debug productivity. Main Responsibilities: Designed and executed functional and design validation flows for advanced RG NAND devices using silicon and simulation platforms Developed deterministic usage‑case tests and random sequence generators to validate NAND commands and customer‑mode features Performed electrical failure analysis of issues seen, root‑cause investigations (including digital and analog circuitry), and drove issue resolution with cross-functional teams Characterization of NAND performance including timing and power parameters, with the latest NAND ONFI interface standards Conducted simulation studies using Verilog and Synopsys VCS to suppor