Senior Silicon Power Engineer Jobs

About the Team The Consumer Products team at OpenAI builds end-to-end hardware and software systems that bring AI into the physical world. We work at the intersection of custom silicon, embedded systems, operating systems, and cloud services to deliver reliable, production-ready devices at scale. Within Consumer Products, the camera stack is a critical sensing component. The team partners closely with electrical engineering, silicon vendors, systems, and higher-level perception and product teams to bring up new hardware, stabilize capture pipelines, and ensure camera systems are robust, debuggable, and ready for real-world deployment. This work spans early prototypes through production, with a strong emphasis on correctness, repeatability, and long-term reliability. About the Role As a Camera Firmware Engineer, you will own low-level camera enablement on custom hardware—from early board bring-up through stable production capture. You will develop and maintain the firmware and software that makes camera sensors reliable, controllable, and debuggable, forming the foundation for higher-level camera pipelines and product features. This role is highly hands-on and systems-oriented. You will work close to the hardware, diagnose real-world timing and integration issues, and build tooling that accelerates iteration across the entire camera stack. This role is based in San Francisco, CA. We follow a hybrid work model with four days per week in the office and offer relocation assistance to new employees. In This Role, You Will Bring up new camera sensors and modules on prototype and production boards, including link stability, sensor control, and correct power, reset, and clock sequencing. Develop and maintain low-level camera software, including sensor drivers, board configuration, and camera subsystem integration across hardware revisions. Enable and validate core capture paths for development and production, including RAW capture for debugging, still capture, and hardware-

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, dynamic, share a sense of humor, and collaborate extensively to push the boundaries of what is possible. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are seeking an experienced Senior Manager to lead Product Co-Design and Verification in areas of Speed, Reliability and Power Compliance. You will oversee speed/timing/reliability system design, Simulation-to-Silicon power/speed verification, features for product compliance and test chip development crating future product roadmaps. The ideal candidate will have deep technical expertise in semiconductor/VLSI design and a background in translating product requirements into design and vice versa. This is a highly visible, multi-functional role to produce outstanding products that ship at SOL and meet the high NVIDIA quality we demand and customers expect. <p

Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation, and this role exists to close it. You wouldn't be maintaining existing solutions, you'd be identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely. The problems here don't have known answers yet: Every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens. What you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards. Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting an

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a

Since 2003, Entrata has evolved from a visionary, student-led startup into a global leader in AI-driven property management technology. Today, we power the industry's most essential operating system, serving owners and residents worldwide through a comprehensive suite of intelligent leasing, payment, and communication tools powered by cutting-edge AI. With a proven track record of sustained growth and a global team of more than 2,200 employees, we offer the rare combination of established stability and high-velocity innovation. Recognized by the Silicon Slopes Hall of Fame and the Utah Business Fast 50, Entrata fosters a culture of radical transparency and entrepreneurial energy. At Entrata, we create an environment where different perspectives are valued and respected. Those perspectives challenge assumptions, strengthen our decisions, and raise the bar as we reshape the global living experience through AI-powered solutions. We are seeking a Senior Data Scientist to help improve the quality and performance of Entrata’s AI models and applications. This role will focus on fine-tuning strategy, training data, experimentation, evaluation, and identifying the approaches that produce the best outcomes for complex property management workflows.

NVIDIA is seeking a world-class computer architect to contribute to the development of future high-performance computing systems, with a focus on enhancing the power-constrained performance of the hardware. Ideal candidates will have a strong track record of understanding and analyzing memory systems architecture to improve performance per watt (perf/W) and performance per millimeter (perf/mm). A broad perspective across the field of computer architecture and depth in the area of power, performance, and area (PPA) analysis is highly desirable. NVIDIA has pioneered programmable GPUs and the CUDA language and is a world leader in high-performance computing technology, with aggressive plans for future processors. This position offers the opportunity to have a real impact in a fast-moving, technology-focused company. What you will be doing: Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro-architecture features to improve the state-of-the-art in GPU memory systems, optimizing along the axes of perf/W, perf/mm, and perf/$. Develop and enhance architecture prototype models for power and noise analysis. Participate in performance and power simulation of features to analyze, define, and improve energy per byte. Analyze benchmarks, application workloads, and performance/power simulation and emulation results to identify areas for architecture optimizations. Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. Collaborate with outside partners on system infrastructure. What we want to see: 10&#43; yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. Bachelor

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

About the Team OpenAI’s Legal team plays a crucial role in advancing our mission by tackling novel and consequential legal issues in AI. The commercial infrastructure legal team supports the systems and facilities that make advanced AI possible, including compute, first-party silicon, colocation, and first-party data center development. About the Role We’re seeking a senior commercial infrastructure lawyer to lead legal work across our rapidly growing data center development and colocation portfolio. You will advise on complex, high-value transactions involving new data center sites, power, construction, colocation, and related infrastructure arrangements. This role is designed for a lawyer who understands how data centers are developed and operated—not a general real estate practitioner. You will work closely with infrastructure, finance, procurement, and operations teams, while coordinating outside counsel where appropriate, to help projects move quickly and responsibly. San Francisco is preferred, and occasional travel may be required. In this role, you will: Lead commercial legal strategy and risk management for data center development and colocation transactions. Draft, negotiate, and advise on colocation agreements, construction agreements, power-related arrangements, and other contracts supporting data center development. Support first-party projects involving raw land, site and power rights, design and construction, EPC models, third-party build-to-suit structures, and leasebacks. Partner cross-functionally with infrastructure, finance, procurement, operations, and other stakeholders on fast-moving, complex projects. Manage and collaborate effectively with outside counsel across a high volume of infrastructure matters. Develop scalable legal playbooks and contracting approaches for a growing portfolio of data center sites. You might thrive in this role if you have: 12+ years of legal experience, primarily in commercial legal roles. Deep, hands-on experience

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle. What you will be doing: Own end-to-end manufacturing test methodology across all test stages. Translate system specs and product POR into DFP requirements, test content, coverage, and flows. Define and maintain the DFP roadmap, including infrastructure and turning point planning. Partner multi-functionally to implement test content, debug hooks, and coverage improvements. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. Embed testability requirements into design to enable robust screening and debug. Define data and analytics frameworks to support yield analysis and continuous improvement. Lead DFP documentation as the single source of truth and feed findings into future methodologies. What we need to see: MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 6&#43; years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. <

Senior Silicon Photonics Design Engineer — California, Santa Clara. Apply via Workday.

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

Senior DFT - Silicon Validation Engineer — CA, Santa Clara. Apply via Workday.

Senior CPU Pre-Silicon Verification Engineer — 2 Locations. Apply via Workday.

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

Senior Engineer, NAND Silicon Design Validation — MSB, Singapore. Apply via Workday.