Senior Silicon Validation Methodology Engineer Jobs

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI,

NVIDIA is seeking a Senior System Architect to define two foundational areas of the GPU: the mechanisms that manage GPU execution state and the register address and access architecture used across the processor. This hands-on role spans architecture, functional modeling, verification, hardware and software integration, and silicon bring-up. We collaborate across ASIC, firmware, driver, verification, and performance teams to guide features from early exploration through implementation and validation. The resulting architecture will build GPU responsiveness, reliability, scalability, software compatibility, and the way increasingly sophisticated processors are configured and managed. What you’ll be doing: Architect and evolve GPU context-management mechanisms, including efficient methods for saving and restoring execution state. Own the GPU-wide register address map, coordinate address allocation, resolve conflicts, and maintain a scalable architecture through multiple product iterations. Define requirements, interfaces, compatibility expectations, and on-die and cross-die interconnects for register access and programming. Develop C++ functional-model support and collaborate with hardware build, embedded software, device software, testing, and performance groups to translate architectural requirements into coordinated solutions. Evaluate tradeoffs across performance, area, complexity, scalability, reliability, compatibility, and development effort. Build validation strategies, debug cross-stack issues through pre-silicon validation and initial silicon testing, and improve the tools and automation supporting register-interface development. What we need to see: A bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a similar field, or equivalent experience. 5+ years of proven experience in computer archit

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role Overview The ASIC Test Engineer is responsible for test program development, silicon validation, yield analysis, and production test optimization for advanced ASIC/SSD controller products. This role supports both NPI and HVM phases, driving fast ramp, robust quality, and cost-effective test solutions across wafer sort and final test. Key Responsibilities Develop and debug ATE test programs for wafer sort and final test (probe to package) to support silicon bring-up and production ramp. Drive yield analysis, failure characterization, and root cause investigation to accelerate yield improvement and ensure product quality. Collaborate with design, product engineering, reliability, and OSAT teams to resolve test and silicon issues across the product lifecycle. Optimize test coverage, test time (TTR), and cost through test content development, guardband tuning, and screening strategy improvements. Support hardware bring-up including probe cards, load boards, and tester configurations to ensure stable manufacturing operations. Enable efficient NPI execution by developing scalable test solutions and improving cycle time from bring-up to HVM. AI/Advanced Data Capability Apply AI/ML and data-driven methodologies to enhance yield analysis, anomaly detection, and failure classification. Leverage AI-assisted tools (e.g., code generation, debug automation, data analytics platforms) to improve engineering productivity and debug cycle time.<br

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior/Staff Engineer, NAND Product Development in Non-Volatile Engineering (NVE) group at Micron Technology, Inc., you will be responsible for test flow development and testing strategies with emphasis on Test Chips for Micron’s pioneering 3D NAND memory. You will be collaborating with multiple teams like Test Solutions Engineering on test code development, Design Engineering on testmode implementation, and validating and debugging testmodes and test results via simulation and post silicon validation of the tests. Provide critical test solutions that will be used to screen the quality and reliability failures on Micron’s NAND products. Responsibilities: NAND Testchip test flow development and validation Run pre si Verilog (Digital) and Analog design simulations to verify testmodes. Define and improve post si testing methods to address new experimental designs, process or debug issues on devices manufactured at Micron’s R&D and Fab10 Manufacturing facilities Perform device characterization and electrical failure analysis (EFA) Collaborate with Test Solutions Engineering on test code development. Collaborate with Design Engineering on testmode implementation, pre si verification and post si validation of testmodes. Collaborate with Process Integration, yield engineering to improve overall die yield and meet the critical turning points planned for the Testchip. Leverage AI tools to automate the tools and workflow</

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. About the Role We are looking for a passionate and innovative ATE Test Engineer to design and deliver cutting-edge test solutions for HBM-DRAM devices using modern advanced ATE platforms. In this role, you will lead the development and implementation of test plans, ATE test programs, silicon validation, and test methodologies, while driving multi-site hardware design and development, product characterization, and high-volume production support. Success in this position requires a forward-thinking mindset and the ability to apply the right technologies to meet evolving challenges. Key Responsibilities Develop and implement robust test strategies, plans, and ATE programs for HBM-DRAM devices. Drive silicon validation, characterization, and yield improvement initiatives. Design and debug test hardware, including schematic capture and PCB layout. Collaborate cross-functionally to ensure seamless integration of test solutions into production. Support high-volume manufacturing and troubleshoot complex test issues. Qualifications & Skills Education: Bachelor’s or Master’s degree in Electrical, Electronics or Computer Engineering. Experience: A

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. We are looking for an Engineer/Senior Engineer in Product Engineering, NAND Functional and Design Validation Infrastructure (FDV-Infrastructure) , experienced in silicon validation, failure analysis, and infrastructure development. Strong focus on automation, data‑driven validation, and leveraging AI to improve test efficiency, coverage, and debug productivity. Key Responsibilities: Design and execute functional and design validation flows for advanced RG NAND devices using silicon platforms Develop and maintain test program infrastructure , including deterministic usage ‑ case tests, random sequence generators and new NAND interface. Implement automation frameworks using C ‑ based programming, Python, and Perl to improve test development and execution efficiency Apply AI/ML ‑assisted techniques (data analytics, pattern recognition, anomaly detection) to: Accelerate failure triage and root ‑ cause analysis workflows I

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Senior Emulation Engineer Location: India - Remote Job Description: At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. Responsibilities: • Set up and maintain Siemens Veloce emulation and prototyping platforms • Adapt SoC designs for Emulation and Prototyping • Develop and debug emulation testbenches and system-level environments • Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. • Collaborate with design and verification teams to isolate design issues and accelerate debug. • Optimize performance of the emulation workloads and reduce turnaround time. • Work with firmware/software teams to enable use of emulators for OS and driver testing. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) • Experience with emula

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing! What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines. Architect features to help silicon debug and support post-silicon validation activities. What we need to see: Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science. 8&#43; years of meaningful work experience. Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digita

We are seeking a highly versatile Sensor & Hardware Safety Engineer to bridge the gap between rigorous hardware reliability and real-world system behavior. In this hybrid role, you will be responsible for 50% hardware-level Functional Safety (ISO 26262) and 50% system-level sensor safety (SOTIF / ISO 21448). You will ensure that our custom hardware meets strict ASIL compliance while guaranteeing our advanced sensor suites (Cameras, LiDAR, Radar) operate safely through perception edge-cases and environmental challenges. In This Role, You Will: Evaluate supplier technical documentation for advanced imagers, microprocessors, and SoCs to verify SEooC and AoU alignment. Assess vendor deliverables to guarantee ASIL standards are met for firmware/software maturity and diagnostic systems. Execute board-level FMEDA for sophisticated integrated circuits, including FPGAs and microcontrollers. Partner with Software, FW, and EE departments to define architectural requirements that enhance diagnostic monitoring. Support the V&V team in developing SOTIF-compliant simulation and physical test protocols for edge-case scenarios. Qualifications Minimum of a B.S. in Automotive, Robotics, Aerospace, or Electrical Engineering. At least 3 years of professional experience involving board bring-up, silicon validation, or hardware design. Understanding of SOTIF and ISO 26262 safety protocols. Strong interpersonal and professional communication capabilities within a collaborative environment Bonus Qualifications ISO 26262 professional certification (CFSP or CFSE). Background in automotive-grade hardware validation and design. Experience utilizing traceability platforms like JAMA or Polarion. Familiarity with industry standards including IEC 61508, DO-254, and DO-178C during board bring-up.

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from a diverse group of backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a senior validation lead engineer to lead at-scale rack validation efforts for next-generation AI hyperscale systems. This role focuses on post-silicon system validation across the full lifecycle, ensuring functional, electrical, and thermal performance meets product objectives. You will own end-to-end blade and rack validation including planning, development, execution, and debug while collaborating across firmware, systems, and hardware teams. The Team The Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Responsibilities and Duties Lead post-silicon validation of AI compute blades and racks including test planning, development, and automation. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness. Own execution against program achievements and report validation progress and risks. Triage test failures, collect debug data, and collaborate on root cause analysis. Track

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our team develops the innovations that power AI, mobile, and computing platforms around the world. Our DRAM Engineering team brings together experts across design, verification, manufacturing, and product development to solve complex technical challenges and deliver advanced memory solutions. We are passionate about innovation, collaboration, and building technology that enables the next generation of computing. As a Semiconductor Design Engineer, you will help develop advanced DRAM and emerging memory products from concept through silicon validation. This role offers opportunities to contribute across circuit design, simulation, verification, and optimization while working closely with global engineering teams. Depending on experience, you may also lead technical projects, mentor engineers, and influence future memory design strategies. Responsibilities: Design, simulate, and optimize digital, analog, and mixed-signal circuits for DRAM and emerging memory products. Translate product requirements into circuit solutions and validate performance across operating conditions. Perform circuit verification, silicon correlation, debug, and tape-out support activities. Collaborate with design, verification, layout, CAD, product, and process teams to improve product quality and manufacturability. Contribute to design automation, AI-assisted workflows, technical reviews, and engineering protocols. Minimum Qualifications: <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Engineering Program Manager with proven experience leading ASIC/SoC development programs, responsible for coordinating multi-functional deliverables across Micron. The role requires end‑to‑end ownership of ASIC development—from architecture and RTL through verification, PnR, integration, and silicon validation—along with strong project planning skills in estimation, scheduling, and milestone dependency management. Job requirements: BS/BEE in Electrical or Electronics Engineering with 7&#43; years of experience. Experience in ASIC/SoC design and development programs. Proven track record of delivering ASIC products end‑to‑end. Strong understanding of the ASIC design flow. Experience driving risk management, change control, and development reviews. Familiarity with ISO 9001 requirements; experience with FuSa and ISO 26262 is encouraged. Experience coordinating programs across multiple, global organizations. Strong proficiency with program/project management tools. Apply AI-enabled engineering tools Job Function: Responsible for end‑to‑end program execution of semiconductor devices, ensuring schedule, power, and cost targets are met. Drive risk management, change control, development reviews, and compliance with ASIC development processes. Regularly report to senior management on key achieve