Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d
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Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Mask Development team within Micron’s Technology Development organization delivers reticle solutions that help enable the next generation of memory and storage products. We work at the intersection of advanced lithography, materials science, and precision manufacturing to solve complex patterning challenges. If you enjoy collaborating with technical experts, driving innovation, and making a direct impact on product quality and technology advancement, you’ll find exciting opportunities here! As a Resolution Enhancement Techniques (RET) Engineer, you will help develop and optimize RET and Optical Proximity Correction (OPC) solutions that enable high-fidelity wafer patterning for advanced memory technologies. Depending on experience and qualifications, candidates may be considered for Principal, MTS, or SMTS-level roles. This position partners closely with teams across technology development and manufacturing to improve reticle solutions, enhance tapeout methodologies, and solve critical patterning challenges that support Micron’s technology roadmap. Responsibilities: Develop and implement RET and OPC solutions to improve pattern fidelity, manufacturability, and yield Optimize lithography methodologies, software capabilities, and tapeout processes to improve performance and efficiency Analyze patterning issues, identify root causes, and drive corrective actions across R&D and manufacturing environments Lead complex mask development and lithography optimiza
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