Soc Compute Memory Subsystem Architect Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience. You have hands-on experience with industry-standard DFT tools such as Synopsys and Siemens, as well as scripting in TCL and Python. You bring expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of inserted DFT logic. You are a strong cross-functional collaborator who can assess risk, communicate resource needs, and deliver in a complex technical environment. What we need Build

Opportunity Overview: We’re looking for a Compliance Analyst to help our team ensure our compliance processes are consistent, scalable, and sustainable as the organization grows. Our team provides centralized ownership and management of the compliance programs by collaborating cross functionally across the organization. You’ll also partner closely with IT and People Operations to ensure the organization operates in accordance with legal, regulatory, and ethical standards. What you’ll do: Support execution of HITRUST, HIPAA, and SOC 2 readiness, certification, and re-certification activities. Assist in remediation of identified deficiencies of gap assessments.. Implement and monitor security controls aligned with HITRUST CSF and related standards. Provide guidance on HITRUST frameworks, MyCSF tool usage, and best practices. Collaborate with IT, security, and compliance teams to ensure smooth certification processes. Prepare and present audit findings and compliance reports to leadership. Support internal training programs to strengthen compliance awareness. Required Qualifications: Education : Bachelor’s degree in Information Security, Risk Management, or related field. Experience : 2 + years in compliance, Access control, ISO or HITRUST-related projects. Preferred Skills Familiarity with GRC tools and cloud security. Knowledge of major compliance frameworks (SOC 2, ISO 27001, GDPR, NIST, HIPAA). Strong analytical, communication, and stakeholder management skills. ISMS roles and responsibilities ( Entry to 5 yrs) Fair understanding of Information Security practices. Align to the organization policies and procedures. Ensure to get updated with ISMS roles as assigned by the department/process heads. Ability to commute/relocate: Hyderabad, Telangana: Reliably commute or planning to relocate before starting work (Preferred) Interview Process*: Connect with Talent Acquisition Meet with the Hiring Manager Behavioral Interview(s) Case Study Interview

Perplexity is continuing to rapidly scale our Enterprise Engineering Organization and seeking Engineering Managers with deep expertise across the Enterprise domain to help lead the next wave of growth. As an Enterprise Engineering Manager, you will combine technical judgment, product intuition, and people leadership to help large organizations adopt AI at scale. We are hiring across the enterprise control plane, enterprise data plane, and connector marketplace and activation. Depending on your area of focus, you will lead and grow a team in one of these areas, addressing challenges such as: Enterprise Control Plane : Building the identity, security, and governance foundations that enable large organizations to deploy Perplexity confidently, including SSO, SCIM, role-based access, customer-managed encryption keys (BYOK), admin APIs, and enforceable policies governing access to data, models, and tools. Supporting regulated-industry requirements, including SOC 2, HIPAA, data governance, and residency, with audit logs and analytics that give administrators visibility into how Perplexity is used. Enterprise Data Plane : Building the connector platform and semantic data layer that give Computer reliable, permission-aware access to enterprise systems and knowledge, including managed authorization, private-system access, and data freshness. Connector Marketplace and Activation : Building discovery, recommendations, onboarding, and marketplace experiences that help customers find and adopt integrations, while working with partners to expand the connector ecosystem. Across these areas, you will translate enterprise customer needs into scalable technical solutions across Perplexity’s products. Responsibilities Set technical direction for your team and guide architecture decisions across the enterprise platform. Build the foundational systems that enable large organizations to deploy Perplexity broadly and confidently. Shape roadmaps with product and design, applying strong tec

Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will be responsible for creating and optimizing the Register Transfer Level (RTL) design for System-on-Chip (SoC) projects. You will integrate logic of IP blocks and subsystems into complete SoC designs, ensuring power, performance, and timing requirements are met. Your work will play a critical role in delivering high-quality designs that enable Intel products to excel in cutting-edge technologies. Business Group Intel Corporation is a global leader in semiconductor innovation, enabling advancements in computing and connectivity. This role is within our System-on-Chip (SoC) design engineering team, which focuses on developing high-performance, reliable, and secure solutions. Join a group that drives technology leadership and supports Intel's mission to power a world enriched by data. The primary responsibilities for this role will include, but are not limited to: Develop RTL designs for SoC, integrating IP blocks and subsystems into full chip designs. Participate in defining architecture and microarchitecture features for design blocks. Perform quality checks on logic design aspects, ensuring convergence in timing, power, and functionality. Apply strategies and tools to optimize logic for power, performance, area, and timing goals. Review verification plans to validate design features and resolve issues in RTL tests. Follow secure development practices to address security requirements within designs. Work with IP providers to integrate and validate IPs at the SoC level. Drive quality assurance compliance for smooth IP-to-SoC handoff. Qualifications: Minimum Quali

About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands-on engineering, and creative approaches to building complex hardware. About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre-silicon validation, silicon bring-up, and post-silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end. In this role, you will: Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products. Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules. Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust

Reports to: Senior Manager, Product Support Location: Remote Ireland Compensation Range: €32,000 to €42,000 base, plus bonus and equity. *This role requires Tuesday-Saturday work days.* What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 11M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. What We Do: Huntress is a fully remote, global team of passionate experts and ethical badasses on a mission to break down the barriers to cybersecurity. Whether creating purpose-built security solutions, hunting down hackers, or impacting our community, our people go above and beyond to change the security game and make a real difference. Founded in 2015 by former NSA cyber operators, Huntress protects all businesses—not just the 1%—with enterprise-grade, fully owned, and managed cybersecurity products at the price of an affordable SaaS application. The Huntress difference is our One Team advantage: our technology is designed with our industry-defining Security Operations Center (SOC

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next‑generation HBM logic die and memory‑centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry‑leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints. This role combines full-chip physical verification ownership — including DRC, LVS, ERC, and DFM — with deep collaboration across implementation and silicon bring‑up, ensuring design integrity from layout through first silicon. Responsibilities will include, but are not limited to: Implement physical verification sign‑off for full‑chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM). Implement and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in clos

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations. Ideal Background: An ideal candidate will have: Experience with full ownership of the specs and drove implementation for at least one SoC/die A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks Nice to Have: Experience with multi-die/multi-chiplet/MCM designs Experience with reticle-max/large-die SoC architecture Understanding of levers available for improving PPA Track record of very high speed A0 silicon delivery

Role Summary We are seeking an experienced SOC / Security Operations Lead to oversee and strengthen the organization's Security Operations Center (SOC), threat detection, incident response, vulnerability management, data protection, and security monitoring capabilities. The ideal candidate will possess extensive experience in managing enterprise security operations, SIEM/SOAR platforms, threat hunting, incident response, DLP, endpoint security, and vulnerability management programs. The role requires leadership of a multi-functional security operations team responsible for protecting critical business systems, customer data, and digital assets while ensuring compliance with RBI regulations and industry security standards. Key Responsibilities Security Operations Center (SOC) Management -Lead and manage 24x7 Security Operations Center (SOC) functions. -Establish and enhance SOC processes, playbooks, escalation procedures, and operational metrics. -Ensure timely detection, triage, investigation, containment, and remediation of security incidents. -Develop SOC maturity roadmaps aligned with industry best practices and regulatory expectations. -Monitor security KPIs, SLAs, MTTR, MTTD, and incident response effectiveness. SIEM, XSIAM & Threat Detection -Lead implementation, administration, and optimization of: -Palo Alto Cortex XSIAM -SIEM Platforms -SOAR Platforms -UEBA Solutions -Threat Intelligence Platforms -Develop and tune correlation rules, detection logic, and analytics use cases. -Enhance detection coverage across cloud, endpoints, applications, networks, and third-party environments. -Drive threat hunting and proactive security monitoring initiatives. Incident Response & Threat Management -Lead enterprise cyber incident response activities. -Develop and maintain incident response plans, runbooks, and communication procedures. -Coordinate investigations involving malware, ransomware, phishing, insider threats, account compromise, fraud, and adv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a SoC Architecture and Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the architecture, design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, design, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role for candidates passionate about architecture, RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Architect, design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Trans

As a SOC Engineer / Detection Engineer, you will be responsible for detecting, investigating, and responding to security incidents across our environment, while continuously improving how we detect and handle threats. You will work hands-on with our SIEM and incident response processes, and act as a key point of contact between the SOC and other engineering/security teams. Depending on your profile, some of your responsibilities can include: - Incident Response: Lead and support the end-to-end response to security incidents, from detection through containment, eradication, and recovery. - Security Investigation: Conduct in-depth investigations into suspicious activity and alerts, correlating data across logs, endpoints, network, and cloud sources to determine root cause and impact. - Post-Mortems & RCAs: Drive post-incident reviews and root cause analyses (RCAs), documenting timelines, findings, and actionable follow-ups. - SIEM Engineering: Implement, tune, and maintain SIEM use cases, detection rules, correlation logic, and alerting to reduce false positives and close detection gaps. - SIEM Support: Provide ongoing support for the SIEM platform, including onboarding new log sources, troubleshooting data ingestion, and maintaining dashboards/reports. - Cross-Team Collaboration: Partner with Engineering, IT, and other Security teams to remediate findings, validate fixes, and share threat context. - Process Improvement: Identify gaps in detection, response, and documentation, and drive improvements to playbooks, runbooks, and SOC workflows. **Must have:** - Incident Response: Hands-on experience handling security incidents, including triage, containment, and coordination across teams. - Investigation Skills: Strong analytical ability to investigate alerts and logs (SIEM, EDR, network, cloud) and determine root cause.