Soc Compute Memory Subsystem Architect Jobs

What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 16M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. Reports to: Engineering Manager Location: Remote US Compensation Range: $200,000 - $220,000 base plus bonus and equity What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconn

What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 16M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. Reports to: Director, Engineering Location: Remote US, Only Compensation: $215,000 to $240,000 base plus bonus and equity What You’ll Do: Huntress is building an Agentic SOC. When our detection pipeline raises a signal, an LLM-based agent picks it up and investigates it end-to-end. It gathers telemetry across our products, reconstructs what happened, and makes a well-documented determination about whether the activity is malicious. Over time, it will take on more of the work itself, growing from resolving routine cases to acting fast when it finds an attack and handing analysts cases with the evidence already assembled. We’re hiring a Principal Software Engineer to head this effort. This system is meant to augment our analysts, not replace them. It takes the high-volume, repetitive work off their plates so they can focus on complex cases and hands-on keyboard intrusi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Technical Program Manager to help drive the execution of complex SoC and chip-development programs supporting RISC-V CPU servers, machine learning processors, and memory and I/O chiplets. Working closely with the lead TPM and engineering owners, you will make project work visible, track owners and commitments, coordinate dependencies, surface risks, and keep teams moving toward their development milestones. This is a technical program role focused on design and development execution; it does not own engineering decisions or create or approve the project budget. Prior semiconductor experience is helpful, but candidates from software and other technical-development environments are welcome and can learn the SoC domain in the role. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You are organized and able to turn complex discussions into clear actions, owners, priorities, and concise status updates. You take ownership of project follow-through, proactively identify blockers, and can influence technical stakeholders without relying on direct authority. You communicate firmly and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions that enable advanced AI, high-performance computing, data center, and networking applications. Our team collaborates across architecture, RTL design, verification, physical design, firmware, and product engineering to deliver innovative memory-centric SoC solutions that meet demanding power, performance, area, quality, and schedule objectives. As an HBM SoC Design Engineer/Architect, you will contribute to the design, integration, and validation of advanced HBM logic die and memory-centric SoCs. Working alongside experienced engineers, you will apply knowledge gained through academic coursework, research, internships, and engineering projects to solve real-world semiconductor design challenges. This role offers opportunities to develop expertise in digital design, ASIC development, HBM architecture, and AI-enabled engineering methodologies that improve design productivity and quality. Responsibilities Design, implement, and integrate digital logic and subsystem RTL using Verilog or SystemVerilog for next-generation HBM SoC solutions. Collaborate with architects and multi-functional engineering teams to translate functional requirements into microarchitectures, interface definitions, and implementation plans. Support design-quality activities including simulation, synthesis, static timing analy

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Physical Design team is responsible for implementing advanced High Bandwidth Memory (HBM) SoC and base die designs that enable next-generation AI, high-performance computing, and data center solutions. The team collaborates across architecture, RTL, verification, DFT, and signoff engineering to deliver high-performance, power-efficient silicon while developing innovative design methodologies and automation solutions. As an SoC Physical Design Intern on the HBM team, you will work alongside experienced engineers to support the implementation of advanced HBM SoC designs. You will gain hands-on experience with physical design methodologies, timing analysis, signoff flows, and automation while contributing to the development of next-generation memory products that power AI and high-performance computing applications. Responsibilities Support the physical implementation of SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, and physical optimization activities. Analyze timing, power, area, congestion, and physical verification results to find opportunities for design improvement and optimization. Assist with static timing analysis, timing closure, and debugging across multiple operating modes and process corners. Develop and enhance automation tools, scripts, reports, and workflows using Python, Tcl, shell scripting, and AI-assisted solutions. Collaborate with multi-functional engineering teams to document r

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job responsibilities: · Create SoC Verification plan and develop C/SV/UVM based SoC verification tests · Develop understanding on SoC Architecture and Test controller Architecture · Develop SV / UVM based testcases for Test controller verification, MBIST verification and Functional vectors generation · Develop SV/UVM monitors to measure performance and improve Verification Environment · Interact with Architecture/Design/Tester teams to identify ASIC test vectors and functional patterns requirement · Develop flows to automate verification environment development and drive team · Involve in Vectors Bring-up activity and support ATE/Tester teams for Functional Characterization Job Qualifications · Bachelors/Masters in Engineering. · Minimum 7&#43; years of SOC/IP Verification based on SV/UVM. Proficient in using AI tools and Methodologies · Good understanding on Test controller / MBIST / DFT architecture · Knowledge of industry standard interfaces, such as PCIE, LPDDR*, ONFI/NAND is desired. · Proven experience in ATE/Functional CHAZ vector enablement in Silicon / Wafers and debug abilities on vectors <p

Staff Design Engineer - SOC — Singapore. Apply via Workday.

Principal Engineer – ASIC SoC Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Intern - HBM SoC RTL Design Engineer — Folsom, CA. Apply via Workday.

System Software Engineer – GPU and SOC (2027 RDSS Intern) — Taiwan, Taipei. Apply via Workday.

Staff/Principal Engineer - Design Verification (SoC expert/lead) — San Jose, CA. Apply via Workday.

What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 16M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. Reports To: Director of Product Management, Platform Location: Remote US Compensation: $190,000 to $220,000 base plus bonus and equity About The Role: We are building a product management organization to own and drive our product strategy, and we are looking for an experienced product manager to own a new team focused entirely on Security tooling for the Huntress SOC. Our SOC is the cornerstone of the Huntress Security Platform, serving SMB and mid-market clients through MSP/MSSP and Reseller channels. It delivers premium, human+AI services at a scale most companies can't match — Rapid Response, Tactical Response, and Hypercare together accounted for roughly 150 engagements in a single recent month. Much of that delivery still runs on an internal SOC platform that does not match analysts' current needs - this includes spreadsheets, Slack threads, and per-engagement documen

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Member of Technical Staff, SoC Power and Physical Architect in the Next-generation HBM Architecture Team, you will drive SoC-level specification 3D-stacked, high-performance memories. Apply your knowledge to analyze SoC trade-offs in close collaboration with peer architecture and design teams. Drive power architecture, physical planning, and early SoC design activities, including definition of IP interfaces (e.g., signals, power delivery), clocking, power sequencing, design-for-test, floorplanning, and specification development. Responsibilities: Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces. Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation. Define DFT architectures (e.g., scan chain topology) and set verification requirements. Define SoC floorplans in collaboration with physical designers. Compose and maintain clear SoC physical documentation. Preferred Qualifications: Experie

Engineer 4, SOC, Comcast Business — TX - Plano, 7900 Windrose Avenue 8th Floor. Apply via Workday.