Soc Static Timing Analysis Engineer Jobs

What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 16M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. Reports to: Senior Manager, Security Operations Center Location: Remote Australia Compensation Range: $110,000 to $140,000 AUD base plus bonus and equity What You’ll Do: You’re a hands-on SOC Analyst who thrives on detecting and responding to cybercrime. You’ll triage Active Hands-On Keyboard intrusions, track attackers through networks, and help remove them before they achieve their objectives. You’ll contextualise endpoint telemetry, analyse logs, leverage forensic artifacts, and understand malware to uncover the full scope of an intrusion. You give a $ht about protecting customers and improving how the team operates, taking ownership of investigations and acting on the information available. You bring Warrior Spirit to complex incidents, staying resilient and composed under pressure. You are Outcome-Obsessed, measuring your work by the threats contained, customers

Replit is the agentic software creation platform that enables anyone to build applications using natural language. With millions of users worldwide, Replit is democratizing software development by removing traditional barriers to application creation. We are looking for a Security Operations Lead (SOC Lead) to build, mature, and operate our 24/7 detection and response capabilities across a modern cloud-native and AI-driven environment. This role leads the global SOC function—monitoring, SIEM ownership, detection engineering, alert triage, and operational readiness—while also evaluating and integrating emerging AI-based SOC products and autonomous response platforms . You will oversee monitoring across multi-cloud environments (GCP primary, AWS/Azure secondary), Kubernetes, SaaS services, endpoints, developer tools, and AI workloads . You’ll collaborate closely with Cloud Security, Compliance/GRC, SRE, Platform Engineering, IT/Endpoint teams, and AI Infrastructure to ensure our detection strategy scales and stays ahead of evolving threats. This is a hands-on leadership role perfect for someone who wants to shape the SOC of the future while solving complex challenges in a high-scale AI setting. What You’ll Do SOC Leadership & 24/7 Monitoring Lead, mentor, and scale a global SOC team responsible for 24/7 monitoring, alert intake, triage, correlation, and escalation. Build operational rigor: processes, runbooks, SLAs, metrics, and quality standards for high-scale environments. Cover monitoring across: Cloud infrastructure (GCP, AWS, Azure) Kubernetes/GKE/EKS/AKS clusters SaaS platforms (Google Workspace, GitHub, Slack, Okta, etc.) Endpoints (macOS, Linux, Windows) including EDR/XDR telemetry Developer platforms + CI/CD pipelines AI/ML systems and model-serving workflows AI-Based SOC Integration & Innovation Evaluate, adopt, and integrate AI-native SOC technologies for triaging, detection, and correlation Identify opportunities to automate triage, investigations,

Drata is building the trust layer between great companies - automating compliance, managing risk, and helping organizations prove trust continuously as they scale. We're Dratanauts: a global crew of 600+ professionals united by a culture that rewards integrity, ownership, and raising the bar, no matter where in the world we're working from. Why Join the Drata Team? At Drata, you're not maintaining legacy compliance software - you're building the agentic AI platform defining what trust looks like for the next generation of companies. Here's what makes the work itself worth showing up for: Problems without a playbook: You'll work at the edge of AI and security, building agentic governance, continuous compliance, and real-time trust verification to solve problems that don't have an established answer yet. You're writing it as you go. Real ownership, not just process: Our values center on owning outcomes and raising the bar, not checking boxes. You're expected to have opinions and back them. A seat at the table: Your perspective is unique and valued. Open debate and diverse viewpoints are built into how decisions actually get made here, at every level. Growth at rocketship speed: Drata is scaling fast, which means scope grows fast too. High performers get more ownership, visibility, and experience. A crew, not just coworkers: Dratanauts consistently describe a "come as you are" culture with sharp, curious people—the kind of team that makes hard problems genuinely fun to solve. See what they say here and follow us on LinkedIn for company news, employee stories, and career updates. Job Summary: Drata's AI Platform team builds the production infrastructure that powers AI features across our compliance platform — from MCP servers that make Drata's data available to AI agents, to LLM workflow orchestration that automates SOC 2, TPRM, and policy analysis. You'll own the systems that sit between our AI models and our customers: tool definitions that agents actually understand,

itD is seeking a Verification Engineer to support the development and verification of next-generation System-on-Chip (SoC) solutions. The ideal candidate will have 5–12 years of design verification experience with expertise in UVM, SystemVerilog, and ASIC/SoC verification, along with a proven ability to deliver high-quality silicon solutions. Location: 100% onsite in Allentown, PA or Carlsbad, CA . Pay Rate: PA: $34.00–$34.20/hr | CA: $41.00–$41.40/hr, depending on experience. We provide comprehensive medical benefits, a 401(k) plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities: Develop and maintain UVM-based verification environments for ASIC/SoC designs. Create and execute block- and system-level verification plans. Design verification components, including assertions, agents, traffic generators, and scoreboards. Partner with cross-functional engineering teams to define verification strategies and improve design testability. Debug and resolve complex design and verification issues throughout the development lifecycle. Perform timing and gate-level simulations to validate design functionality. Support post-silicon bring-up through C-based firmware development and verification activities. Internal Responsibilities: Attend regular internal practice community meetings. Collaborate with your itD practice team on industry thought leadership. Complete client case studies and learning material (blogs, media material). Build out material to contribute to the Digital Transformation practice. Attend internal itD networking events (in person and virtual). Work with leadership on career fast-track opportunities. Required Qualifications and Skills: Bachelor's degree in Electrical Engineering or a related field. 5–12 years of ASIC or SoC design verification experience. Strong experience developing UVM-based testbenches. Proficiency with SystemVerilog. Experience

What We’re Looking For: We’re looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems. Ideal Background: Experience leading DFT efforts for multiple advanced node SoC tapeouts Nice to Have: Experience leading DFT efforts for large die area (eg reticle-max) chips Experience leading DFT efforts for multi-die/multi-chiplet/MCM designs Experience leading DFT efforts for AI accelerator SoCs

Work Flexibility: Hybrid Position Summary The Network Security Engineer is responsible for designing, reviewing, implementing, and supporting enterprise network security architectures to protect the organization’s infrastructure, applications, and external connectivity from cybersecurity threats. This role combines strong network security engineering and architecture expertise with hands-on cybersecurity operations experience. The ideal candidate can independently assess network security risks, design appropriate security controls, and support security investigations in collaboration with Cybersecurity, SOC, and Incident Response teams. The role focuses on securing Internet-facing applications, DMZs, extranets, third-party connectivity, network segmentation, and enterprise security boundaries. This is a cybersecurity-focused engineering position, not primarily a network infrastructure support or firewall administration role. What will you do: Design, review, and implement secure network architectures for enterprise, cloud, hybrid, and remote environments. Evaluate and secure DMZs, extranets, Internet-facing applications, third-party connections, and external access pathways. Identify network security risks and define appropriate technical controls, including firewall policies, segmentation, access restrictions, encryption, monitoring, and compensating controls. Establish and maintain security zones, network segmentation, and trust boundaries to reduce unauthorized access and lateral movement. Engineer and manage enterprise security technologies, including Next-Generation Firewalls (NGFW), VPN, IDS/IPS, Network Access Control (NAC), and related perimeter security solutions. Investigate suspicious network activity and support cybersecurity incident response by analyzing firewall

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Firmware Engineer at Micron Technology, Inc., you will build groundbreaking high-performance controller firmware for volatile and non-volatile memory systems. You will assist in the evaluation, creation, build, bench testing, debugging, and failure analyzes of firmware for new high-performance memory controllers and Solid State Drives (SSD) that will improve performance, while reducing power, latency and SoC (System on Chip) complexity for the target sectors. You can expect to partner multi-disciplinary Engineers seek multi-functional product development issues. You will triage failures, file bug reports, use AI Supported and help the development teams with isolating issues. Job Responsibilities 12+ Years in Firmware Storage/SSD would be a strong plus. Strong firmware design and debug experience using assembly and C programming. Knowledge of mass storage interface protocol PCIe/NVMe, Understanding of storage interfaces including SATA, or SAS (optional) Strong skill in ARM development tools and IDE such as Eclipse Knowledge in the use of scripting languages, programming tools and environments Experience in the storage industry in SSD, HDD, storage systems, or a related technology. Working knowledge of NAND flash and other non-volatile storage is optional but plus. Experience in test equipment such as oscilloscopes and logic/bus analyzers (good to have). Ability to work independently with a minimum of day-to

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff SSD Firmware Engineer at Micron Technology, Inc., you will build groundbreaking high-performance controller firmware for volatile and non-volatile memory systems. You will assist in the evaluation, creation, build, bench testing, debugging, and failure analyzes of firmware for new high-performance memory controllers and Solid State Drives (SSD) that will improve performance, while reducing power, latency and SoC (System on Chip) complexity for the target sectors. You can expect to partner multi-disciplinary Engineers seek multi-functional product development issues. You will triage failures, file bug reports, and help the development teams with isolating issues. 6-15 Years in SSD/Storage Firmware Development would be a strong plus. Strong firmware design and debug experience using assembly and C programming. Knowledge of NAND flash, SSD flash translation layer, wear leveling, garbage collection. Knowledge on backend SLC, MLC, QLC concepts in the architecture of solid-state drives (SSDs) and flash memory. Knowledge of mass storage interfaces such as SATA, SAS, NVMe (optional but strong plus). Knowledge of configuring and debugging issues from the usage of register settings of ASICs in an SoC and embedded firmware dev environment High level of skill in problem recreation and trapping, and in identifying performance critical algorithms for optimization. Strong skill in ARM development tools and IDE such as Eclipse Ability to scope and esti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff SSD Firmware Engineer at Micron Technology, Inc., you will build groundbreaking high-performance controller firmware for volatile and non-volatile memory systems. You will assist in the evaluation, creation, build, bench testing, debugging, and failure analyzes of firmware for new high-performance memory controllers and Solid State Drives (SSD) that will improve performance, while reducing power, latency and SoC (System on Chip) complexity for the target sectors. You can expect to partner multi-disciplinary Engineers seek multi-functional product development issues. You will triage failures, file bug reports, and help the development teams with isolating issues. 6-15 Years in SSD/Storage Firmware Development would be a strong plus. Strong firmware design and debug experience using assembly and C programming. Knowledge and experience of NAND flash, SSD flash translation layer, wear leveling, garbage collection. Knowledge of mass storage interfaces such as SATA, SAS, NVMe (optional but strong plus). Strong knowledge of Flash Translation Layer (FTL) and SSD firmware concepts. Knowledge of configuring and debugging issues from the usage of register settings of ASICs in an SoC and embedded firmware dev environment High level of skill in problem recreation and trapping, and in identifying performance critical algorithms for optimization. Strong skill in ARM development tools and IDE such as Eclipse Ability to scope and estimate developmen

Reports to: Vice President, Channels and Alliances Location: Remote Australia What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M+ endpoints and 15M+ identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. What You’ll Do: Huntress is looking for a Reseller Sales Manager to join our new reseller sales team. In this role, you will be responsible for developing and managing reseller partnerships in Australia & New Zealand to support Huntress' continued growth and expansion. You will use your knowledge of the security landscape to open opportunities and build key partner relationships with resellers at the regional and national level(s). This role will work closely with senior sales leaders and other stakeholders on the revenue team to determine the actions necessary to identify opportunities for new routes to market to increase both revenue and the company’s market presence. You will work to identify value creation opportunities, shape and align implementation and support the resell

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Reports to: Manager, Sales Development Location: Remote Australia What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M+ endpoints and 15M+ identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. What You’ll Do: As a Sales Development Representative here at Huntress, you’ll be part of a small but elite team of reps focused on building and expanding our presence within the Australian market. Our Sales Development Representatives will identify potential net-new accounts and engage with already qualified accounts to convert them into meetings for our Account Executive sales team. This role requires both outbound cold calling as well as handling inbound opportunities. You’ll also share our value proposition and answer any questions that arise during the process in a timely manner. Huntress approaches sales as an opportunity to educate our partners through the value we bring. We rely on our SDRs to generate and qualify leads, make outbound calls, and follow up. Respo

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

Are you ready to contribute to world-class innovation and push the boundaries of what's possible? At NVIDIA, you'll have the opportunity to be part of a team that is driving groundbreaking impacts across various markets. As a Thermal Solutions Development Engineer, you will play a pivotal role in our Silicon Codesign Group, transforming thermal solution concepts into lab-ready builds and beyond. What you will be doing: Build thermal solutions for engineering characterization and validation of next-gen GPU/SOC products, ensuring flawless delivery from concept to lab. Drive end-to-end development and deployment of thermal solutions, collaborating with internal teams and external vendors on build requirements, prototype evaluation, test system integration, and software automation. Improve thermal design processes by incorporating feedback and findings, developing workflow and maintaining our world-class standards. Work closely with system architects, chip and board designers, and software/firmware engineers in a dynamic and high-energy environment to bring industry-defining products to market. Apply AI-enabled approaches and AI tools to accelerate design iteration, test planning, and characterization/validation triage (e.g., requirements/spec summarization, experiment prioritization, log/telemetry summarization, anomaly/outlier detection), improving cycle time, coverage, and traceability while validating outputs against physics, specs, and lab measurements. Partner with AI/tooling teams as the thermal domain SME to define use-cases, success criteria, and evaluation methods; provide feedback to improve tool reliability and usability. What we need to see: