Sr Logic Design Engineer Jobs

Sr. Logic Design Engineer — 3 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design/Senior Design Engineer – NAND digital (NVE Engineering) Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. department Introduction The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with cross-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. Position Overview As a Logic Design Engineer in the NVEG organization at Micron Semiconductor Italia, you will play a key role in the definition, implementation, verification, and silicon validation of NAND Flash logic features. In this role, you will act as a technical owner of complex logic functionalities, working at the intersection of architecture, firmware, datapath, analog, and test teams. You will contribute to new product pathfinding, ensure robust feature implementation across technology generations, and support silicon bring‑up, validation, and learning. Responsibilities Responsibilities include, but are not limited to: • Own end-to-end development of logic features, from architecture definition through RTL implementation, verification, and post-silicon validation. • Translate system and firmware requirements into micro-a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products. Responsibilities Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets. Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities. Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality. Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios. Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market. Minimum Qualifications Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products. Responsibilities Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets. Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities. Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality. Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios. Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market. Minimum Qualifications Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Engineer in the FLASH Group at Micron Technology, Inc., will be core technical individual contributor in design and validation of the on-chip controller and mixed signal circuitry in NAND FLASH chips. In this highly visible and challenging role, your responsibilities will include architecture development and product definition, detailed transistor level design, test plan, system integration and verification. Some RTL design and implementation of the controller hardware, design and development of firmware code for NAND internal operations and full-chip Verilog Validation. Successful candidates must have: Solid knowledge in Verilog language. Solid digital logic fundamentals. Basic understanding of analog circuits. An understanding and knowledge with mixed-mode design and validation. Through understanding of Design/Verification CAD tools such as ncsim, Design Compiler, Formality, PrimeTime, etc. Knowledge of TCL or PERL. Knowledge in non-volatile memory design (NAND in particular) is a strong plus. Using AI or AI proficiency is a plus About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performan

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have developed an outstanding team stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: You will document, implement, and deliver fully verified, high performance, area and power efficient RTL to achieve the design targets and specifications. Your responsibilities will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. In addition to the design role, you will participate in the verification of the design using sophisticated verification methodologies. You are expected to help define the verification scope and support the development of verification infrastructure. You will collaborate with several ASIC development teams and will need to communicate and coordinate with members of those teams, some of whom are in remote locations. What we need to see: A Bachelors or Masters Degree (or equivalent experience) 5+ years of relevant / meaningful work experience Proven hardware engineering background with a concentration in VLSI and Computer Architecture Expertise in Verilog, System Verilog or similar HDL. Proficient programming in Perl/Python

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode

Opportunity Overview: We’re seeking a Senior Clinical Informatician to serve as a key bridge between clinical expertise and data science. In this advanced role, you’ll apply deep clinical reasoning and informatics expertise to design, evaluate, and optimize data-driven healthcare solutions. You’ll also lead ontology mapping, structured data validation, and annotation quality initiatives supporting our next-generation AI and LLM-enabled healthcare tools. This is a remote-first role that may require travel to Boston, MA for new hire onboarding and occasional in-person team meetings and company events. What you’ll do: Collaborate with clinicians, data scientists, and engineers to design and validate digital health and analytics solutions. Translate clinical workflows into structured data and logic for algorithms and quality measurement. Lead efforts in ontology mapping, terminology management (SNOMED, ICD, LOINC, RxNorm), and interoperability standards (FHIR, HL7). Oversee labeling and abstraction to ensure model safety, accuracy, and clinical integrity. Mentor junior informaticians and specialists in annotation, data validation, and workflow improvement. What you’ll need: BSN or related clinical degree with active RN license required. 4–6+ years of experience in clinical informatics, analytics, or digital health. Advanced understanding of clinical data, EHR systems, and data standards. Experience with data modeling or AI-driven healthcare products preferred. Master’s degree or informatics certification (RN-BC, CPHIMS, ACHIP, etc.) a plus. Pay & Perks: 💻 Fully remote opportunity with about 5% travel 🩺 Medical, dental, vision, life, disability insurance, and Employee Assistance Program 📈 401K retirement plan with company match; flexible spending and health savings account 🏝️ Up to 184 hours (23 days) of PTO per year + company holidays 👶 Up to 14 weeks of paid parental leave 🐶 Pet insurance The salary range for this p

GAQ226R75 About the Role We are looking for a Senior Full Stack Developer to design, build, and deploy modern, scalable AI agents and applications that leverage Large Language Models (LLMs). This role requires a strong focus on end-to-end agent development, including building a high-performance React frontend, designing the agentic logic in Python, integrating with backend services, and ensuring production readiness. Key Responsibilities: Design, develop, and deploy AI agents for business-critical workflows, with a focus on LLM orchestration and tooling. Implement complex agentic behaviours using frameworks like LangChain or LangGraph, including ReAct loops for reasoning and action. Design and develop a high-performance React application for the agent's user interface. Collaborate with backend teams to integrate APIs and services, and build tools for agents. Work with middleware (Python/Node.js) to orchestrate agent calls and data flow. Implement comprehensive observability and tracing for agent runs and system performance. Build reusable, scalable UI components. Optimise application performance, responsiveness, and scalability. Participate in architectural discussions and contribute to solution design. Write clean, maintainable, and testable code with proper documentation. Required Skills & Experience 5+ years of experience in full-stack development, with strong expertise in Python and React.js . Proven experience in designing, building, and deploying at least 1 production-deployed AI agent or LLM application . Deep expertise in LLM orchestration, prompt engineering, and utilizing tools/plugins to extend agent capabilities. Experience with agent frameworks like LangChain or LangGraph , including implementing reasoning patterns like the ReAct loop . Experience with observability, logging, and tracing for AI agents. Experience building large-scale, enterprise-grade applications. Strong experience with API integration (REST/GraphQL). Experience working in Agile/Sc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles and Responsibilities · Plan and execute verification of analog and mixed-signal circuits at block, subsystem, and full-chip levels. · Develop and maintain full-chip mixed-signal simulation environments in which analog circuitry, digital logic, and firmware coexist. · Create schematic and behavioral models for selected blocks to make full-chip simulations feasible, efficient, and sufficiently accurate for the intended verification objective. · Develop verification plans from design data sheets, new feature requests, requirements, interface definitions, and identified risk areas. · Run static and dynamic simulations to identify leakage paths, power-sequencing issues, and unintended circuit interactions. · Perform device-level electrical rule checks, including SOA, snapback, SFB, and related reliability checks. · Perform SPF extraction analysis and fanout, connectivity, and coupling checks. · Execute power-cycling simulations, including power-loss and brownout events. · Run chip-level user-mode simulations that correlate analog subsystems, logic behavior, and firmware algorithms. · Debug complex AMS failures with a system-level outlook, identify root causes, and work with design, firmware, and verification partners to drive closure. · Develop scripts and reusable automation for regression setup, simulation execution, log processing, waveform analysis, result comparison,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles and Responsibilities · Plan and execute verification of analog and mixed-signal circuits at block, subsystem, and full-chip levels. · Develop and maintain full-chip mixed-signal simulation environments in which analog circuitry, digital logic, and firmware coexist. · Create schematic and behavioral models for selected blocks to make full-chip simulations feasible, efficient, and sufficiently accurate for the intended verification objective. · Develop verification plans from design data sheets, new feature requests, requirements, interface definitions, and identified risk areas. · Run static and dynamic simulations to identify leakage paths, power-sequencing issues, and unintended circuit interactions. · Perform device-level electrical rule checks, including SOA, snapback, SFB, and related reliability checks. · Perform SPF extraction analysis and fanout, connectivity, and coupling checks. · Execute power-cycling simulations, including power-loss and brownout events. · Run chip-level user-mode simulations that correlate analog subsystems, logic behavior, and firmware algorithms. · Debug complex AMS failures with a system-level outlook, identify root causes, and work with design, firmware, and verification partners to drive closure. · Develop scripts and reusable automation for regression setup, simulation execution, log processing, waveform analysis, result comparison,

Celonis is the trusted platform to industrialize Enterprise AI. At our core is the Celonis Context Model — which combines process data, business knowledge, and intelligence into a living digital twin of the enterprise that AI can actually understand, turning AI's operational blind spots into operational clarity. World's leading companies trust Celonis and its global ecosystem of partners to make their AI agents, people, systems, and processes work together, achieving transformational outcomes. We believe there's a massive opportunity to unlock global productivity and sustainability by giving AI the context to understand how every business process really works. Join our mission to make processes work for people, companies, and the planet. The Team Prisma is a newly formed team building the Modeling Library that powers Celonis' Process Modeling Experiences. This library is the foundation for how users create, edit, and visualize process models across the platform. The team works closely with Product, UX, and other engineering teams to turn complex modeling and graph problems into fast, intuitive interactions for our customers. The Role As a Senior Software Engineer on Prisma, you'll help build and grow the Modeling library from the ground up. You'll work on the graph rendering, layout, and interaction logic that lets users model business processes clearly and efficiently, even with large and complex data sets. We're looking for engineers who already use AI coding tools daily and know how to apply them to solve real engineering problems fast, not as a novelty, but as part of how they build production-quality software. The work you'll do Design and build the Modeling library's core components using TypeScript, Angular, and HTML5. Solve complex visualization problems such as fast interactions, dynamic graph layouts, and graph interactions, to Celonis' quality bar Use AI coding tools daily to speed up development and problem-solving on graph layout, rendering, and in

For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day. Smartsheet maintains certifications and attestations across SOC 2 Type II, the ISO 27001/27017/27701/22301 suite, HIPAA, and other commercial compliance frameworks—and the manual work of proving those controls quarter after quarter doesn't scale with the business. We're looking for a Sr. Security Engineer I to bring an engineering mindset to our commercial GRC program: automating control monitoring, building evidence pipelines, and reducing the audit-season scramble into a default state of readiness. You'll work hands-on with our GRC platform, cloud, and identity tooling to make control evidence collect itself wherever possible, and you'll partner closely with engineering teams to translate compliance requirements into technical control logic they can actually build against. This is a builder's role within GRC—less checklist administration, more systems thinking applied to compliance. Our approach is grounded in GRC Engineering principles: automate early and often, treat controls and their mappings as code, favor continuous assurance over periodic checks, and build compliance that engineers can consume as easily as they contribute to it. This role reports to the Senior Director, GRC Engineering and can be based in our Bellevue, WA office or remotely from anywhere in the US where Smartsheet is a registered employer. You Will: Own control automation for SOC 2, ISO 27001/27017/27701, HIPAA, and related commercial frameworks: design and build automated evidence collection and continuous control monitoring across cloud, ident