Staff Dram Semiconductor Design Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of DRAM Memory array/Peripheral Logic/Analog circuits Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate schematic optimization and design‑space exploration Assist in parasitic analysis, sensitivity studies, and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom methodology for memory design Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments. Oversee and manage the layout process including floor-planning, placement, and routing Perform circuit-level verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools. Contribute to cross-group communication to work towards standardization and group success Drive innovation into the future memory generations and design methodology within a dynamic work environment Minimum Qualifications Master’s degree in electrical or computer engineering with 15+ years of experience in vlsi design. Strong fundamentals in CMOS circuit design, device physics and memory operation. Proven lea

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. About the Role As a Member of Technical Staff (MTS) in Micron’s HBM Product Engineering Component Validation team, you will serve as a technical leader and authority for the validation of advanced High Bandwidth Memory (HBM) products. You will apply deep DRAM and HBM architecture and design knowledge to define validation coverage strategy, lead complex product debug and failure analysis, and drive a zero-escape validation mindset across all test modes and product milestones. Operating within Micron’s global validation organization and partnering closely with teams across multiple sites, you will influence design-intent-to-coverage decisions, mentor engineers, and set the technical direction for current and next-generation HBM validation. Responsibilities and Tasks Technical Leadership & Validation Strategy Act as a technical authority for HBM Component Validation, translating DRAM/HBM design intent and architecture into comprehensive validation coverage and test strategy. Define and own validation methodologies and coverage plans across structural (black-box) and functional test flows, driving toward full validation coverage at each product milestone with zero validation escapes. Lead validation definition and closure for new and high-risk product

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Frontend Central Product Integration Engineering (PIE) team delivers best‑in‑class yield, quality, and cycle time through innovation and strong cross‑functional teamwork. Supporting diverse DRAM and NAND technologies across global development and manufacturing sites (Boise, Japan, and fabs in the U.S., Taiwan, Japan, and Singapore), the team identifies, aligns, and deploys best‑known methods across the network. As a Frontend Central Process Integration Senior Engineer, you will develop and optimize processes to drive rapid product maturity. Join us today and make a difference! Responsibilities and Tasks Drive rapid product maturity, improving yield (bits per wafer), repair density, and DPM through fast learning cycles. Apply deep process integration knowledge across FEOL, MOL, CELL, and BEOL to identify optimal solutions; design and circuit knowledge is a plus. Partner with Yield Engineering, Device, RDA, and Metrology teams to resolve key yield issues and build strong inline visibility for fast ramp and excursion prevention. Identify and standardize best‑known methods and business processes across DRAM and NAND sites. Travel to Micron sites as needed for onsite collaboration. Minimum Qualifications Bachelor’s degree in Engineering or a related field 5+ years of experience in process integration, product design, or equivalent technical roles Demonstrated ability to collaborate optimally with global, cross‑functional teams Proven t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning. In depth knowledge of processes across different loops or functions (FEOL, MOL, CELL, BEOL) to identify best optimum process integration solution to achieve the goal, knowledge on product and circuit design will be plus. Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to enable fast yield ramp and minimize excursion. Identify best known method and business process from DRAM/NAND sites and drive for alignment and standardize across network. Travel to Micron sites as necessary for face to face collaboration. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations tha

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. 【募集職種/Position Title】 Senior / Staff / Principal Process Development Engineer 【日本語】 MicronのDRAM Technology Development Process Development Teamは、MicronのDRAMおよびHBM (High Bandwidth Memory) 製品向けのプロセス技術、装置ソリューションを開発する、世界最高水準のエンジニアと技術専門家で構成された組織です。 当チームでは、先端DRAM、HBM、およびCMOS技術の開発を推進しており、リソグラフィ、CVD、ドライエッチ、ウェットプロセス、メタライゼーション、拡散、イオン注入、CMP、先端材料開発など、幅広いプロセス分野で経験豊富な人材を募集しています。 本ポジションでは、ユニットプロセス技術の探索、開発、最適化を担当し、プロセスインテグレーション、デバイス、設計エンジニアと連携しながら、装置メーカーや材料サプライヤーと協働して、次世代のDRAMおよびHBM向けの高性能かつコスト競争力のある技術開発を推進していただきます。 本ポジションでは、半導体プロセス開発、デバイス物理、CMOS技術に関する高度な知識が求められます。また、データ解析能力や材料分析、表面解析技術への理解も重要です。チームワークと高いコミュニケーション能力は、本職務で成功するための重要な要素となります。 歓迎する技術経験 以下の技術分野における実務経験をお持ちの方を歓迎します。 ・成膜技術 (CVD、ALD、PVD) ・エピタキシャル成長技術 (Si、SiGe、選択成長など) ・ゲートスタックおよび誘電体技術 ・先端パターニングおよびドライエッチ技術 ・ウェット洗浄および表面処理技術 ・イオン注入および熱処理技術 ・コンタクト形成、配線メタライゼーション技術 ・化学機械研磨技術 (CMP) ・ストレスエンジニアリングおよび先端材料統合技術 ・先端トランジスタ開発を含むロジック技術開発 ・メモリCMOSおよび周辺回路向けプロセスインテグレーション技術 主な職務内容 以下を含みますが、これらに限定されません。 ・デバイス、プロセスインテグレーション、および製品要求事項の理解 ・技術目標およびコスト目標達成に向けたプロセス技術ロードマップおよびサプライヤー戦略の策定 ・開発環境および量産環境におけるプロセスレシピの開発、最適化 ・構造解析、材料分析、および電気特性評価データの解析 ・デバイス性能、歩留まり、信頼性、およびコスト競争力向上に向けた技術革新の推進 ・AI（人工知能）を活用した開発業務の効率化、高度化の推進 ・社内関係部門および外部パートナーとの連携による複雑な技術課題の解決 ・技術戦略および開発方針に関する経営層への提言 ・エンジニアの育成、指導を通じた組織能力の向上 ・高い倫理観、オーナーシップ、および他者への敬意を持った業務遂行 応募資格（必須） ・電気工学、物理学、化学工

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Frontend Central Product Integration Engineering team strives to deliver leading edge process capability, best-in-class bits per wafer (Yield) with highest quality and fastest speed through innovation and collaboration with cross functional team. With the diversity of technology in DRAM/NAND and geography (TD development sites – Boise/Japan, 5 manufacturing sites – US (F6, ID1), Taiwan (OMT), Japan (F15) and Singapore (F10)), Frontend Central PIE team will be responsible to identify best-known-method holistically, align best-known-method timely and implement improvement systematically across the network. As FE Central Process Integration Senior Engineer, you will be responsible to develop best optimum process to achieve product maturity. Responsibilities and Tasks: Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning. In depth knowledge of processes across different loops or functions (FEOL, MOL, CELL, BEOL) to identify best optimum process integration solution to achieve the goal, knowledge on product and circuit design will be plus. Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to e

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking an experience high-speed high-speed IO/Clocking Design Engineering at a Principal/Sr Member of Technical Staff (SMTS) level to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop core strategy and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation resu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the CMOS Device Integration Team at Micron, where we push the limits of memory technology every day. We work at the intersection of device physics, process integration, and product performance to enable the next wave of DRAM, HBM, and Compute-in-Memory innovation. If you’re excited by challenging technical problems and real-world impact, you’ll feel right at home here! In this role, you’ll serve as a technical leader shaping the future of Micron’s most advanced memory products. As a Distinguished Member of Technical Staff, you’ll drive CMOS device and module development that directly impacts array efficiency, data rates, and product scalability. Your expertise and influence will help guide technology decisions that power AI, high-performance computing, and emerging applications. Responsibilities: Develop and integrate advanced CMOS devices for next-generation DRAM, HBM, and emerging memory architectures Perform detailed electrical characterization of CMOS devices and circuits to drive performance improvements Partner with Design, TCAD, Modeling, Process, Reliability, and Layout teams to deliver integrated technology solutions Provide technical leadership, strategic recommendations, and clear presentations to guide technology direction Minimum Qualifications: Master’s degree or PhD in Electrical Engineering or equivalent practical experience 10 or more years of hands-on experience in advanced CMOS device design and/or integration 1

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Summary The role requires a Member Technical Staff who has broad experience and innovative thinking. This person will lead the improvement of Diffusion, Thin Film Deposition (PECVD/PVD), and Wet Etch processes in advanced DRAM technology nodes. This role is critical to enabling manufacturing requirement memory products. It requires strong process integration expertise , strategic vision, and leadership capabilities. You will drive innovation, lead technical initiatives, define technology roadmaps, and mentor engineering talent. The focus is on improving process capability and accelerating yield ramp . Key Responsibilities Coordinate all activities related to the characterization, and refinement of Diffusion, PECVD/PVD thin film deposition, and Wet Etch processes for advanced DRAM applications. Collaborate cross-functionally with Integra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Member of Technical Staff HBM Design Architect, you will be responsible for design and development of high-speed interface between DRAM and Base die in HBM cube! This includes designing the DRAM command and control logic, as well serializing and de-serializing scheme. You will collaborate with a highly creative and motivated development team applying brand-new memory technologies to build groundbreaking HBM products! Responsibilities: Responsible for the high-speed DRAM and Base die interface in HBM cube. Design the DRAM command and control logic, as well as serializing and de-serializing scheme at the interface. Conduct circuit simulations using standard industry simulators such as FINESIM, HSPICE and VERILOG Collaborate with data path design on floor planning and full chip testbench. Analyze timing/area/power in high-speed DRAM or mixed-signal design. Contribute to the development of new HBM product opportunities by assisting with the overall design, layout, and optimization of Memory, Logic, and Analog circuits. Qualifications: Extensive experience with DRAM operation and JEDEC specifications across DDR, LPDDR, GDDR, and HBM product families. Strong technical expertise in analog and mixed-signal circuit design. Hands-on proficiency in DRAM command decoding, bank logic, and RAS/CAS chain design. Demonstrated innovation and problem‑solving capabilities in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Understand the LPDRAM state machine and develop the hardware models for DRAM features and the related validation test bench. Develop memory controller models, including request scheduling and address mapping to enable new DRAM features. Develop the automation test scripts using Python to improve the overall simulation methodologies. Develop new DRAM technology changes per the spec and the state machine and the validation test bench. Develop system engineering, software engineering, system integration, or distributed system architectures. Identify system data, hardware, or software components required to meet user needs. Communicate with staff or clients to understand specific system requirements. Research, test, or verify proper functioning of software patches and fixes. Provide advice on project costs, design concepts, or design changes. Communicate project information through presentations, technical reports, or white papers. Design and conduct hardware or software tests. Establish functional or system standards to address operational requirements, quality requirements, and design constraints. Evaluate existing systems to determine effectiveness, and suggest changes to meet organizational requirements. Employer will accept a Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or related field. Position requires: 1. C/C++ or Python; 2. Debugging interfaces, including GDB and PDB; 3. LPDRAM technology; 4. Computer Architecture; 5. Memory controller