System Hardware Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Software Driver Developer to create reference drivers for our AI-IP in a reference system. You will also support our AI-IP customer optimizing our reference driver into our customer specific systems. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deep systems engineer with 7+ years of experience in device drivers or low-level systems programming. Strong proficiency in C and C++ with a solid understanding of hardware-software interfaces. Hands-on experience developing Linux kernel drivers, including kernel architecture, debugging, and kernel-space/user-space interactions. Experience developing drivers for high-speed I/O or interconnect technologies such as PCIe; PCIe driver development is strongly preferred. Familiar with user-mode and kernel-mode driver models and understands that Linux kernel driver development differs meaningfully from bare-metal or RTOS-based driver development. What We Need Design and evolve the driver layer that provides high-performance APIs for Tenstorrent devices. Develop and maintain user-mode and kernel-mode drivers for Te

About the job Explore how a next-generation AI architecture behaves from rack scale to data centre scale. As a Senior Systems Engineer, you will investigate a novel AI computing architecture under demanding real-world workloads. You will work on problems where answers aren't readily known, turning curiosity into measurable evidence. You will design experiments, benchmark representative AI workloads and explore how hardware components and software interact at scale. When behaviour is unexpected, you will turn this into new measurements. Your work will help infrastructure engineers, architects and application specialists understand system behaviour, performance, scalability and reliability across the stack. You will also help develop tooling and automation to collect, analyse and visualise system metrics. You do not need to be an AI expert. You will need strong judgement, curiosity and a clear preference for evidence over opinion. You will love this role if you are someone who takes initiative, questions assumptions and enjoys working in areas where the answers are not yet known. The team and culture The System QA team is distributed across multiple locations. We work hard to stay connected and collaborate closely. Our daily team meetings feel more like a virtual coffee break than a formal status update with space to share ideas, ask questions, discuss discoveries and solve problems together. We value trust, autonomy and openness, and we understand that great engineers don't all follow the same career path. What matters is the quality of your work, your curiosity, and your willingness to explore challenging problems. You will have regular 1:1s with your people manager where you will have the opportunity to discuss things that matter to you. You will have dedicated time each week to focus on your CPD. The technical lead will provide direction and help set priorities, but everyone in the team is there to support each other. One of our core principles is tha

Salary Range: (Determined during interview process, based on technical fit for each level of role) Staff Engineer - PLN 350,700 - 474,400 + Benefits + Equity Senior Engineer - PLN 260,400 - 352,200 + Benefits + Equity Subject to alignment to the responsibilities and duties of the role. Location: Gdańsk - Hybrid Working Policy - 3 Days per week in office About the job Explore how a next-generation AI architecture behaves from rack scale to data centre scale. As a Senior Systems Engineer, you will investigate a novel AI computing architecture under demanding real-world workloads. You will turn complex system behaviour into measurable evidence. You will design experiments, benchmark representative AI workloads and explore how hardware components and software interact at scale. When behaviour is unexpected, you will turn uncertainty into new measurements. Your work will help infrastructure engineers, architects and application specialists understand performance, scalability and reliability across the stack. You will also help develop tooling and automation to collect, analyse and visualise system metrics. You do not need to be an AI expert. You will need strong judgement, a clear preference for evidence over opinion and a desire to explore complex systems beyond the obvious. The team and culture The System QA team is distributed across multiple locations so we work deliberately to stay connected. Daily team meetings create space to share ideas, ask questions, discuss findings and solve problems together. You will have regular 1:1s with your people manager where you will have the opportunity to discuss things that matter to you. You will have dedicated time each week to focus on your CPD. The technical lead will provide direction and help set priorities, but everyone in the team is there to support each other. Decisions are guided by evidence, clear communication and a willingness to challenge assumptions. Your manager will trust you to follow the evidence w

Why RoboForce RoboForce is an AI robotics company developing Physical AI–powered Robo-Labor for dull, dirty, and dangerous work. The company’s robots are engineered for demanding industrial environments, with a focus on real-world deployment and scalability. We are looking for a motivated Mechanical Design Engineer Intern to join our team. This is a hands-on opportunity to design, prototype, test, and iterate on robotic hardware for real-world deployment. You will work alongside experienced mechanical, electrical, and robotics engineers on ambitious, real-world problems. You will help turn ideas into tested hardware and see how your designs perform as part of complete robotic systems. Responsibilities Design mechanical parts, mechanisms, and assemblies for robotic systems. Create and update 3D CAD models and engineering drawings . Perform basic engineering analysis, tolerance checks, and FEA. Support prototype fabrication, assembly, testing, and design iteration. Collaborate with mechanical, electrical, and robotics engineers during system integration. Requirements Currently pursuing a Bachelor’s, Master’s, or PhD in Mechanical Engineering, Robotics, Mechatronics, or a related field, or graduated within the past 6 months . Strong mechanical design fundamentals. Experience with SolidWorks or Fusion 360 . Hands-on experience designing and building mechanical hardware through coursework, research, internships, robotics teams, or personal projects. Familiarity with manufacturing processes such as CNC machining, sheet metal, or 3D printing. Able to work on-site in Milpitas, CA, five days per week (40 hours/week) Bonus Qualifications Experience with robotic arms, actuators, transmissions, mobile robots, or end-effectors . Familiarity with GD&T, tolerance stack-up, FEA, and DFM . Machine-shop or rapid-prototyping experience. Experience taking a design from CAD to manufactured and tested hardware . Benefits Company-provided lunch and dinner, a fully stocked

At Lyft, our purpose is to serve and connect. We aim to achieve this by cultivating a work environment where all team members belong and have the opportunity to thrive. Lyft Urban Solutions powers the bike-sharing and scooter-sharing systems that move millions of people in over 60 cities worldwide. We built North America's first automated bike-share system and continue to lead the micromobility revolution. Our systems operate globally - from Citi Bike in New York to BIXI in Montreal, Divvy in Chicago, Capital Bikeshare in DC, and iconic systems in Austin, Barcelona, Bogota, Boston, Buenos Aires, Columbus, Detroit, Dubai, London, Madrid, Mexico City, Monaco, Pittsburgh, Portland, Rio de Janeiro, San Francisco, Toronto, and beyond. We're not just technology providers - we operate these systems, building the software, hardware, and operations that make urban micromobility work at scale. Ready to shape how millions of people move through their cities every day? The Lyft Urban Solutions (LUS) Firmware Engineering Manager role is central to the development and delivery of Lyft's micromobility hardware offerings, including e-bikes, scooters, batteries, charging stations, and more! We are looking for a Firmware Engineering Manager who combines deep technical expertise in embedded systems with strong people leadership to grow and guide a team of firmware engineers. This person will drive the technical roadmap for New Product Introduction (NPI) and fleet sustainability programs, while building the team, processes, and technical culture needed to deliver safe, reliable, and field-proven firmware at scale across the cities that rely on our products. Firmware Engineering Managers at Lyft partner closely with hardware, software, product, data science, manufacturing, operations, and compliance teams, and are expected to bring strong technical judgment, organizational leadership, and clear communication to every level of the business. Responsibilities: Lead, mentor, and grow a team

At Lyft, our purpose is to serve and connect. We aim to achieve this by cultivating a work environment where all team members belong and have the opportunity to thrive. Lyft Urban Solutions powers the bike-sharing and scooter-sharing systems that move millions of people in over 60 cities worldwide. We built North America's first automated bike-share system and continue to lead the micromobility revolution. Our systems operate globally - from Citi Bike in New York to BIXI in Montreal, Divvy in Chicago, Capital Bikeshare in DC, and iconic systems in Austin, Barcelona, Bogota, Boston, Buenos Aires, Columbus, Detroit, Dubai, London, Madrid, Mexico City, Monaco, Pittsburgh, Portland, Rio de Janeiro, San Francisco, Toronto, and beyond. We're not just technology providers - we operate these systems, building the software, hardware, and operations that make urban micromobility work at scale. Ready to shape how millions of people move through their cities every day? The Lyft Urban Solutions (LUS) Firmware Engineer role is key in the development and delivery of Lyft’s micromobility hardware offerings, including electric bikes, scooters, batteries, stations, and more! We are looking for a Firmware Engineer who brings exceptional technical skills to contribute in NPI (New Product Introduction) and fleet sustainability programs that unlock value for the cities across the globe that use our products. Firmware Engineers at Lyft collaborate closely with hardware, operations, and manufacturing teams, necessitating strong technical expertise, leadership, and communication skills. They are proactive problem solvers who drive initiatives forward, ensuring the successful delivery of key results that significantly impact the business. Responsibilities: Develop features for embedded systems across our Micromobility product line(vehicles, docks, internal tools). Work with cross-functional teams to prototype, develop, and take to production, our next generation of world-class mobility produ

Zoox is on an ambitious journey to develop a full-stack autonomous mobility solution for cities and safely deploy such a robotaxi solution. The System Design and Mission Assurance (SDMA) team plays a foundational role in the company's success, responsible for constructing the safety case and fail-operational design for our autonomous driving robots before public road deployment. We are seeking a highly motivated software development engineer in test (SDET). This role is central to leading the creation of automation frameworks, tools, and processes for platform safety clearance and system testing. The ideal candidate is passionate about developing high-quality, robust, optimized, and reusable software infrastructure, and is eager to advance their skills in complex systems thinking and validation problem-solving. Some examples of tools this role has supported in the past: * Front and back end of Streamlit web-app to automate tracking requirements to test case traceability. * Automation framework for execution of safety critical tests. * CI/CD job to identify affected requirements and HIL tests from code changes and automate the execution of all linked tests. In this role, you will: Create tools and web-apps to help us automate and streamline manual clearance processes. Propose tools and/or feature ideas to the team to improve processes. Develop software for automated validation frameworks for system level testing in Hardware In the Loop (HIL), simulation environments, and post-processing of test data. Develop and maintain dashboards to illustrate progress against targets and highlight focus areas. Execute, triage, and debug automated verification and validation system tests. Qualifications B.S. or higher in Mechanical Engineering, Electrical Engineering, Systems Engineering, Computer Engineering, Computer Science or a related technical degree. Experience developing automated test frameworks and tools for

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Firmware Engineer working on microcontrollers and SoCs, focused on low-level C/C++ development and board bring-up. You’ll implement and debug firmware, develop boot/power/reset sequences, and use lab tools to diagnose issues across the hardware–software boundary. You’ll collaborate closely with hardware, board, and system software teams while building strong skills in modern embedded platforms, RTOS/Embedded Linux, and automated testing. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced embedded engineer with a strong foundation in computer engineering, electrical engineering, computer science, or a related field, and a track record of building reliable software for real-world systems. A strong problem solver who enjoys working where software meets hardware and can move comfortably between architecture, implementation, debugging, and system-level thinking. Curious by nature and energized by complex challenges, with a willingness to explore new technologies, development approaches, and AI-assisted tools to make engineering more effective. A thou

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Lead DFT Engineer Job Description: Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements: Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field. Tools:

Zoox is on an ambitious journey to develop a full-stack autonomous mobility solution for cities and safely deploy such a robotaxi solution. The System Design and Mission Assurance (SDMA) team plays a foundational role in the company's success, responsible for constructing the safety case and fail-operational design for our autonomous driving robots before public road deployment. We are seeking a highly motivated V&V software development engineer in test (SDET) to join this systems-engineering department. As a V&V SDET, you will be a technical lead, owning the end-to-end validation strategy for critical safety systems while architecting and implementing the advanced software infrastructure required to verify them. This role is coding-intensive, focused on building solutions for high-fidelity testing, scalable automation frameworks, and sophisticated data analysis tools to ensure successful compliance to requirements and mission success. Some examples of tools this role supports: Framework for event definition, orchestration, and verification High-performance C++ and Python-based emulators for vehicle sensors (e.g., Radar, Lidar, and Inertial Measurement Units) to enable realistic, real-time fault injection Robust communication bridges between simulation environments and physical vehicle hardware Automating test management and reporting within lifecycle management tools, e.g. Polarion, JAMA, DOORS. In this role, you will: Lead the design and maintenance of large-scale event-driven software/hardware -in-the-loop (SIL/HIL) testing frameworks, utilizing advanced software patterns to improve modularity and reduce code duplication. Architect and manage end-to-end continuous integration (CI) pipelines to automate the execution of regression suites. Lead root cause analysis for complex system-level failures, developing log mining scripts and visualization dashboards (e.g., Grafana, SQL-based notebooks) to triage failures and track performance metr

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Description : Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Tools: Mastery of industry-standard

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade. This role is hybrid, based out of Toronto, ON, Austin, TX or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development. Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms. Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines. Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios. Motivated by AI hardware and eager to learn verification strategies for new architectures and domains. What We Need Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning cov

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join our Systems Software Group to lead an engineering team building the core architectural foundation for our high-performance, highly available enterprise storage portfolio. You will own the strategy and execution for core platform software, driving innovations in Linux kernel integration, hardware enablement, and NVMe fabric protocols. Partnering closely with Product, Hardware, and Release Engineering teams, you will empower your team to deliver predictable, high-quality software releases that define the simplicity and reliability our customers trust. WHAT YOU’LL DO Engineering Leadership & Team Development : Lead, mentor, and empower a high-performing systems software engineering team to deliver robust Linux kernel features, hardware platform enablement, and advanced NVMe fabric protocols. Release Execution & Quality Ownership : Own end-to-end software delivery for core platform releases, partnering with Program Management and Release Engineering to establish clear execution roadmaps, milestone tracking, and phased rollout strategies. Partner & Vendor Technical Management : Direct technical engagements with external vendors and technology partners, ensuring third-party deliverables integrate seamlessly into the core platform architecture to accelerate product delivery. Strategic Alignment & Platform Impact : Align team goals with broader business objectives, converting complex architectu

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ is seeking a Senior Power Systems Engineer to drive end to end system architecture, modeling, and optimization for wearable platforms. The candidate will build power models, define system use cases and operating modes, partner with product and engineering teams to meet aggressive power targets, and define manufacturing tests and field telemetry for NPI. The ideal candidate brings strong systems thinking, hands-on experience with low power architectures, and the ability to build models and telemetry to drive tradeoffs from SOC level to board level to maximize user runtime. What You Might Do: Power architecture responsibility for a wearable device covering SoC states, sensor, audio, and memory architecture tradeoffs at board level. Battery, PCM, and charging profile definition and validation Design power experiments, test plans, and measurement & telemetry mechanisms across firmware and hardware to optimize power and performance. Build and maintain system-level power models to model expected power consumption for user profiles. Map power models by subsystem, correlating

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. What You Might Do Lead RF system architecture and integration for wearable and mobile platforms. Own RF desense investigations and mitigation across the product lifecycle. Define RF specifications, link budgets, validation plans and performance targets. Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios. Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance. Perform CST and ADS simula