Xpu Architect Jobs

What We’re Looking For: We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs. Ideal Background: An ideal candidate will have: Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options Deep understanding of AI workloads, especially low latency LLM inference Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: Hands-on experience with AI chip architecture and tapeouts End to end ownership of at least one AI ASIC project History of product delivery (regardless of ultimate commercial success of said product) Experience with HBM-based AI chip architecture Experience in proposing “weird” chip architectures (in any domain, not just AI!)

What We’re Looking For: We’re looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture. Ideal Background: An ideal candidate will have: Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc Understanding of memory sub-systems and interactions in multi-die systems Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems Strongly Preferred: Experience with multi-die designs Experience with MCM and chiplet based architectures and architectural partitioning across them Experience in partitioning workloads across multiple chips and chip packages

Who Are We? Postman is the world’s leading API platform, used by more than 45 million+ developers and 500,000 organizations, including 98% of the Fortune 500. Postman is helping developers and professionals across the globe build the API-first world by simplifying each step of the API lifecycle and streamlining collaboration—enabling users to create better APIs, faster. The company is headquartered in San Francisco and has offices in Boston, New York, Austin, Tokyo, London, and Bangalore - where Postman was founded. Postman is privately held, with funding from Battery Ventures, BOND, Coatue, CRV, Insight Partners, and Nexus Venture Partners. Learn more at postman.com or connect with Postman on X via @getpostman. P.S: We highly recommend reading The "API-First World" graphic novel to understand the bigger picture and our vision at Postman. The Opportunity As a Member of Technical Staff on AI Infrastructure, you will build and maintain the foundational systems and distributed infrastructure that power AI model post training, inference, and data pipelines. You will collaborate with engineering and research teams to ensure performance, scalability, and reliability of critical AI systems. What You’ll Do Design and implement large-scale, distributed AI infrastructure and services Optimize performance for GPU/xPU accelerators and cloud environments Build tools for observability, reliability, and scaling of AI workloads Partner with cross-functional teams to define AI infrastructure

What We’re Looking For: We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal Background: An ideal candidate will have: Hands-on experience with multiple advanced node tapeouts Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts Understanding of PPA improvement and what levers exist for each level of the stack Ability to think creatively about methodology for fast design iterations Nice to Have: Hands-on experience with ASIC design process for large die (ideally reticle max) chips Hands-on experience with ASIC design process for AI chips Hands-on experience with multi-die/multi-chiplet/MCM designs

About the Team The Core Network Engineering team owns the end-to-end networking stack that connects OpenAI’s compute infrastructure — spanning global WAN/edge connectivity, data-center networking, and high-performance host/xPU networking used for large-scale training and inference workloads. This team is responsible for ensuring networking is never the bottleneck to model training efficiency, cluster reliability, or fleet expansion. They design and operate the systems that provide predictable, high-throughput, low-latency connectivity across some of the world’s most advanced AI infrastructure. About the Role We’re looking for engineers to help build and operate the networking foundation behind OpenAI’s frontier AI systems. Depending on your background and area of focus, you may work across host networking, datacenter fabrics, or global WAN infrastructure. The problems span low-level systems software, distributed infrastructure, protocol readiness, observability, performance engineering, automation, and large-scale network operations. You’ll work on systems where microseconds of latency, tail performance, and network reliability directly impact model training efficiency and production serving performance. This role is ideal for engineers who enjoy operating close to the hardware/software boundary and solving performance-critical infrastructure problems at massive scale. In this role, you will: Design, build, and operate networking systems that support large-scale AI training a

About the Team OpenAI’s 1P Hardware Systems team operates at the intersection of Hardware Engineering, Infrastructure, Supply Chain, Manufacturing, Deployment, and Finance to translate infrastructure demand into an executable systems plan. The Planning Lead connects system demand and deployment timing to site and configuration requirements, power availability, XPU needs, hardware supply commitments, manufacturing capacity, and site readiness. About the Role OpenAI is seeking a 1P Hardware Systems Planning Lead to own the integrated demand, supply, and deployment plan for our 1P AI infrastructure systems. This role will connect infrastructure demand and site power availability to system configurations, XPU requirements, and hardware supply commitments—creating a single, actionable view of whether our deployment plan can be met. You will establish the planning mechanisms that allow teams to see what changed, understand the impact, and act quickly when demand, supply, configuration, site readiness, or power timing moves. You will work across Hardware Engineering, Infrastructure, Supply Chain, Strategic Sourcing, Manufacturing, Deployment, and Finance to identify gaps early and drive recovery plans to closure. This is a highly cross-functional role for someone who combines systems-level thinking, strong analytical judgment, and rigorous program execution. The ideal candidate can turn complex and changing inputs into a clear operating plan, surface the decisions that matter, and d