Advanced Package Technology Development Iot Mts Jobs

About the job Build the test systems that prove advanced AI hardware is ready before it reaches production. As a Test Development Engineer, you will create and maintain test systems for Graphcore’s electronic hardware platforms. Your work will support preproduction test solutions across system and board-level products. You will define test methods, specify equipment and automate systems for complex hardware. This includes high-speed serial links, high-current power supplies, slower protocols and low-level PCBA debug. This role sits close to real engineering problems. You will build deep product knowledge, improve test coverage and help transfer robust solutions into production. The team and culture You will join the Hardware Test team, embedded within Graphcore’s wider Hardware Engineering group. The team works closely with SI, mechanical, layout, package, silicon, firmware and production teams. Work moves through practical test design, lab debug, automation and clear data. You will be trusted to take ownership and develop solutions that meet real hardware needs. The team values proactive communication across Graphcore and third-party support teams. Decisions are shaped by evidence, standards knowledge and the quality of the test data. What we’re looking for · Experience developing and automating test systems for complex electronic systems · Knowledge of Ethernet and/or PCIe testing, including high-speed hardware debug · Fluency in test scripting languages, including Python and LabView · Ability to plan test work, improve coverage and communicate progress clearly · Hands-on experience with lab equipment such as oscilloscopes, BERTs and VNAs · Strong ownership, teamwork and communication skills across technical teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate. Benef

Zoox made the world’s first purpose-built commercial robotaxi, combining advanced self-driving hardware and software. In order to ensure safe operation, low latency and consistent resource utilization are critical. The Planner Compute team is responsible for the performance of the largest single software component within the autonomy stack, the motion planner. The Planner Compute team is looking for an expert in GPU performance. You will instrument, monitor, analyze and optimize GPU-based algorithms that are performance-critical for our solution. The scope for GPU usage ranges from machine learning inference to custom CUDA kernels written specifically for the motion planner. In this role, you will: Analyze performance metrics to identify GPU hotspots and optimizations Contribute to the adaptation of our current planner to multiple GPU architectures with different resources Optimize ML models for latency and GPU memory usage Support engineers within Planner as a subject matter expert on CUDA & GPU performance Qualifications BS in computer science or related field and 6+ years of experience. Strong knowledge of CUDA as applied to recent GPU microarchitectures (e.g., Ampere, Blackwell) and experience debugging/optimizing GPU kernels using tools like Nsight. Strong knowledge of C++ and experience in large code bases, comfortable in Linux development environments. Experience in development, debugging, and profiling of complex multiprocess systems (e.g., robotic systems, game engines). Bonus Qualifications GPU kernel development experience There are three major components to compensation for this position: salary, Amazon Restricted Stock Units (RSUs), and Zoox Stock Appreciation Rights. A sign-on bonus may be offered as part of the compensation package. The listed range applies onl

Zoox made the world’s first purpose-built commercial robotaxi, combining advanced self-driving hardware and software. In order to ensure safe operation, low latency and consistent resource utilization are critical. The Planner Compute team is responsible for the performance of the largest single software component within the autonomy stack, the motion planner. The Planner Compute team is looking for an expert in GPU performance. You will instrument, monitor, analyze and optimize GPU-based algorithms that are performance-critical for our solution. The scope for GPU usage ranges from machine learning inference to custom CUDA kernels written specifically for the motion planner. In this role, you will: Analyze performance metrics to identify GPU hotspots and optimizations Contribute to the adaptation of our current planner to multiple GPU architectures with different resources Optimize ML models for latency and GPU memory usage Support engineers within Planner as a subject matter expert on CUDA & GPU performance Qualifications BS in computer science or related field and 8+ years of experience. Strong knowledge of CUDA as applied to recent GPU microarchitectures (e.g., Ampere, Blackwell) and experience debugging/optimizing GPU kernels using tools like Nsight. Strong knowledge of C++ and experience in large code bases, comfortable in Linux development environments. Experience in development, debugging, and profiling of complex multiprocess systems (e.g., robotic systems, game engines). Bonus Qualifications GPU kernel development experience There are three major components to compensation for this position: salary, Amazon Restricted Stock Units (RSUs), and Zoox Stock Appreciation Rights. A sign-on bonus may be offered as part of the compensation package. The listed range applies onl

We’re looking for power integrity engineers to ensure that power is delivered and stable at all levels: rack/tray, package, die, core. Ideal Background: Experience with large die, high TDP chip PDN analysis and design Experience with advanced node (7nm and lower) chip PDN analysis and design Ability to work with package architects to determine best passives design within a given set of constraints Ability to work with ASIC and microarchitecture team to hit power integrity goals given manufacturing design constraints Nice to Have: Experience with WSI (wafer-scale integration) systems Board and system-level power delivery network analysis and design Low voltage die power delivery network analysis and design Many voltage domain power delivery network design and analysis IVR based design experience

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

1891 Signal Integrity Measurement Engineer Location: Austin About the Role Validate signal integrity (SI) and power integrity (PI) for advanced compute platforms, focusing on hands-on measurement, electrical compliance, troubleshooting, and simulation correlation. Key Responsibilities Develop measurement plans and design of experiments (DOE) for board-to-board, cable, backplane, blade-, and rack-level interconnects. Measure scattering parameters (S-parameters), insertion loss, return loss, impedance, crosstalk, eye diagrams, jitter, timing margins, and bit error rates. Design printed circuit board (PCB) test fixtures; perform calibration, de-embedding, and electrical compliance testing against interface specifications and customer requirements. Correlate measurements with simulations and troubleshoot issues with silicon, package, board, and system teams, interconnect vendors, and original design manufacturers (ODMs). Prepare validation and compliance reports covering methods, pass/fail results, performance margins, findings, and recommendations. Required Qualifications Hands-on expertise with vector network analyzers (VNAs), including performance network analyzers (PNAs); time-domain reflectometers (TDRs); bit error rate testers (BERTs); and high-speed oscilloscopes. Strong SI/PI fundamentals and experience with fixture characterization, repeatable measurements, DOE, and electrical compliance testing. Strong written and verbal communication skills for technical reporting and cross-functional collaboration. Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field. Preferred Qualifications Data center or hyperscale hardware experience; Python or MATLAB for measurement automation and analysis; familiarity with simulation tools and thermal or mechanical effects on SI/PI. Tools / Technologies Peripheral Component Interconnect Express (PCIe) generations 4/5/6, Ethernet, Double Data Rate (DDR) memory, serializer/deseria

SIXGEN’s mission is to deliver agile, mission-ready cybersecurity solutions that empower government and critical infrastructure organizations to stay ahead of advanced cyber threats. We combine innovation, deep expertise, and cutting-edge capabilities to uncover vulnerabilities, protect vital systems, and ensure operational superiority in an ever-evolving digital landscape. POSITION OVERVIEW Position: DoW, Account Lead Job Type: Full Time Location: Hybrid. Proximity to DC, Maryland and Virginia required Clearance Requirements: TS/SCI Travel: Up to 25%, depending on your location ABOUT THE TEAM SIXGEN supports cyber and intelligence missions by helping government and commercial organizations overcome global cybersecurity challenges. Our highly skilled operators conduct research and assessments based on real-world threats, simulating adversaries and malicious actors to deliver actionable findings on critical assets and infrastructures. Our program planners advise mission owners to bring rapid solutions to intelligence leaders. Using innovative processes, tools, and techniques, we predict and overcome cybersecurity vulnerabilities. COMPENSATION & BENEFITS SIXGEN offers a competitive executive compensation package, designed to reflect the outsized impact and enterprise value creation expected of this role. The final package will be determined based on experience, qualifications, and demonstrated ability to lead strategic growth. Additionally, SIXGEN offers top-tier benefits for full-time employees, including: Employer-paid health insurance premiums (medical, dental, vision) for you and your family Employer-paid short/long term disability insurance and basic life/AD&D insurance 401K with a 4% employer contribution Professional development reimbursement options available (training, certification, education, etc)​ Flexible and remote work policies for most positions Flexible PTO and holiday schedule OUR COMMITMENT SIXGEN is an Equal Opportunity Employe

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. This role is part of the Customer Engineering Technical Leadership function within HIG PSE. The Customer Integration Engineer will focus on technical engagement across product development, system architecture, develop, front-end and back-end process, Package Failure Analysis, Qualification, and Test. The successful candidate will have expertise in one of these subject areas and a strong appetite to learn others on the job. This position emphasizes hands-on technical problem-solving, working with multi-functional groups, and enabling successful integration of advanced HBM products into customer systems. AI adoptation and regular development and use is a must. Leveraging Artificial Intelligence is part of day to day operations Responsibilities: Apply deep technical knowledge across one or several domains such as product engineering, system engineering, building, front-end/back-end process, PFA, qualification, or test. Support integration of customer requirements into internal design and manufacturing processes. Participate in technical reviews, debug s

What We’re Looking For: We’re looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products. Ideal Background: An ideal candidate will have: Experience leading the architecture of an entire system or subsystem (eg chip, board, die, package) Deep understanding of AI workloads like LLM inference at workload levels and its system level implications Experience with large multicore architectures Nice to Have: Experience with physical design process of large-die area, advanced node chips Experience with multi-die designs such as MCMs and interposer designs

NVIDIA is seeking an a PCB Library Engineer to join our PCB Design Infrastructure team. In this role, you will help develop and maintain the PCB library assets used across NVIDIA's Data Center, AI, Networking, Automotive, and Graphics products. Working alongside experienced PCB designers, library engineers, mechanical engineers, manufacturing engineers, and component engineers, you will create and validate component footprints, schematic symbols, mechanical components, panel definitions, and other critical design assets that enable successful product development. This position provides an excellent opportunity to build expertise in PCB design, manufacturing, component engineering, and design automation while supporting some of the most advanced computing platforms in the world. What you'll be doing: Develop PCB footprints, padstacks, schematic symbols, and mechanical library content using Cadence PCB design tools. Review component datasheets, package drawings, and engineering specifications to create accurate design libraries. Support library verification, release, and documentation processes. Partner with PCB design, mechanical engineering, manufacturing engineering, and operations teams to resolve library-related issues. Learn and apply industry standards, including IPC requirements, DFM, DFA, and DFT principles. Support quality initiatives to ensure library content is accurate, manufacturable, and scalable. Participate in continuous improvement and automation efforts within the library environment. Develop a strong understanding of PCB fabrication, assembly, and component technologies. What We Need to See: BS degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, or a related field or equivalent experience. <p

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron is the place for you to expand your caliber by working on key projects and developing the leader in you! As the Test Solutions Engineer, you will be the key project owner for Micron Nand Flash memory test programs. You will be ensuring project readiness and assessing program quality through stringent program release process. In addition, you will have the following job responsibilities: Develop and maintain wafer and package functional test strategies and programs for semiconductor NAND Flash products Collaborate with various test solutions engineering and production engineering groups to ensure test program, infrastructure and system readiness for new product introduction as well as high volume manufacturing Improve device yield, reliability and quality through test condition optimization, advanced redundancy analysis schemes, data analysis and test equipment hardware optimization Provide cost effective and innovative solutions for production test flow optimization with cutting-edge test time reduction methodologies Assist process and production teams by providing necessary engineering expertise to ensure smooth manufacturing operations Introduce innovative test time reduction solutions and release test pro

Location - Hybrid This is a hybrid role based out of our Gurugram, India office, 3 days in the office, 2 days remote. About Us Sauce Labs is the world’s largest full-lifecycle, test automation platform, and the company behind Selenium. Trusted by 80% of the world’s top ten largest financial institutions and over 300,000 enterprise users, Sauce Labs provides the only AI platform capable of turning business intent into autonomous testing and quality assurance. With a proprietary dataset of 8.7 billion test runs, Sauce Labs empowers the Fortune 2000 to bridge the gap between AI-driven code generation and enterprise-grade software quality. Learn more at http://saucelabs.com . Release Assurance at the Speed of AI | Meet the new Sauce Labs About the Team We’re a small advanced tech team that takes ideas from “someone had a hunch” to “customers are using it”—usually in days, not sprints. This is a high ownership team: talking to whoever has the problem, deciding what’s worth building, cutting scope, shipping, and then deciding whether to double down or move on. Required Skills Deep fluency in at least one modern general-purpose language—and the ability to pick up others quickly. We work across TypeScript/Node, Go, and Python, and you’ll touch more than one. We care far more that you know one language inside out—its type system, concurrency model, testing story, etc.—than that you’ve used our specific stack. An ideal candidate would be comfortable: Reading and modifying an unfamiliar codebase without a guided tour Writing and maintaining tests that hold up in CI, not just on your laptop Publishing and versioning something other people depend on — a CLI, an SDK, a package Debugging across a boundary you don’t own (a third-party API, someone else’s service, a CI runner) Please note our Privacy Policy for Applicants when applying for a job at Sauce Labs. Sauce Labs is proud to be an Equal Opportunity employer and values diversity at our company. We do not discriminate on

SPECIFIC JOB RESPONSIBILITIES Pipeline Management: Maintain high-throughput streaming pipelines to ingest logs from various sources (Firewalls, Cloud, Endpoints) to a central destination. Log Normalization: Write parsers to convert raw, messy logs into standard schemas (e.g., OCSF or ECS) for consistent querying. Cost Optimization: Implement routing logic to send "high-value" data to the SIEM and "bulk" data to low-cost Object Storage (Data Lake). Data Preparation: Clean and structure data to enable AI/ML detection models and advanced analytics. EXPERIENCE REQUIRED Data Engineering: Proficiency in Python (for ETL) and SQL (for complex querying). Streaming Tech: Experience with Message Queues (e.g., Kafka, Pub/Sub) and stream processing concepts. Log Handling: Mastery of Regex and log parsing strategies for standard formats (Syslog, CEF, JSON). Storage Architecture: Understanding of Data Lake principles (Parquet/Avro formats) vs. Data Warehouses. QUALIFICATIONS, SKILLS, & KNOWLEDGE Experience with Vector Databases for storing embeddings. Knowledge of Log Observability/Routing tools (middleware that routes logs). Familiarity with Big Data frameworks (e.g., Spark, Flink). PROFESSIONAL DEVELOPMENT EXPECTATIONS Ability to embrace Clearwater's CLEAR core values (Commitment to Client Success, Lead with Accountability, Integrity & Collaboration, Excellence in All That We Do, Advance Colleague Success, Respect & Transparency) and culture. The base salary range for this role is 35,000- 45,000]. Base salary is part of our total rewards package which also includes the opportunity for merit-based salary increases, eligibility for our 401(k) plan, medical, dental, vision, life and disability insurances and leaves provided in line with your work state. Our robust time-off policy includes flexible paid time off, 11 paid holidays, and paid sick time. Total compensation, including base salary to be offered, will depend on elem

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As the key talent within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will involve in both intrinsic and extrinsic reliability test program coding for Micron’s latest HBM products. Your responsibility is to develop new reliability test flow (eg: extended wafer level burn in, pWLRx, ELFR etc), both on DRAM and Interface die and a stacked product for extrinsic DPM (Time0 and Field DPM) and intrinsic reliability assessment to meet critical KPI’s Quality, Cost and Cycle Time. You will play pivotal role in ensuring the reliability and robustness of our products through advanced coding practices and comprehensive testing. This position demands a strong grasp of engineering principles, adept problem-solving skills, and a relentless dedication to maintaining high-quality standards. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics. Micron is seeking experienced individuals that find technical challenges engaging and invigorating. Responsibilities: Reliability Test Program Coding: Writing and debugging test programs for HBM device and package qualification

About the Team OpenAI is building the world’s most advanced AI infrastructure ecosystem. The Site Readiness & Development team owns the upstream diligence and development work required to convert powered-land opportunities into executable infrastructure options. About the Role The Powered Land Developer will support the advancement of powered-land opportunities across the portfolio, reporting to the Development & Power Project Lead. This is an individual contributor lead role and does not have direct reports initially. This role will own day-to-day development execution across approximately 1–3 active sites depending on complexity, including utility applications, interconnection requests, study follow-through, queue milestones, consultant workstreams, schedule and risk management, and readiness handoff for opportunities advancing to deeper diligence, commercial commitment, or execution. The role translates study and utility findings into clear schedule, budget, and risk implications for portfolio decisions. Responsibilities Manage day-to-day advancement of powered-land opportunities from intake through readiness. Own utility application and interconnection follow-through across active powered-land opportunities, including utility inputs, study responses, and queue milestones. Scope and manage external studies and consultant workstreams needed to validate readiness. Track development schedules, dependencies, risk registers, site-readiness milestones, and key budget implications. Translate technical findings into clear schedule, budget, and risk implications and escalate material blockers or trade-offs to the Development & Power Project Lead. Partner with land, environmental, economic development, and community affairs leads to align project advancement. Support expansion planning, infrastructure sequencing, and long-term power-risk mitigation. Define readiness criteria and prepare handoff packages for opportunities moving into deeper diligence or executio