Advanced Package Technology Development Iot Mts Jobs

Principal/Senior Engineer, Advanced Package Metrology-Real-Time Defect Analysis (MRDA) — Fab 10A, Singapore. Apply via Workday.

Package Architect – Advanced Packaging & System Exploration — 2 Locations. Apply via Workday.

Metro RDA Senior Manager (Package Development for Advanced Packaging) — Fab 10A, Singapore. Apply via Workday.

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development. Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability. Develop, validate, and apply package reliability models and lifetime-prediction

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

About the Role You will contribute to and own aspects of the Volantis A-0 and A-1 package. We are interested in both people with package design as well as package process development backgrounds Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more. We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP. This creates both unique challenges and opportunities. The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. What We Look For Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. What works for 5x reticle platforms may not work for 56x reticle platforms Design or process development of complex packages Nice to Have: Experience with heterogeneous material assemblies Experience with high-TDP packages Experience with compound semiconductor assemblies Experience with co-packaged optics Ability to work with architects to co-design system architecture and package design Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc Experience with flip-chip integration, especially mass reflow, TCB & LAB Experience with large scale (>50x50mm) substrates Compensation Package: Competitive Base salary + Significant Equity Stake. You'll be well compensated while also owning a piece of the outcome. California Pay Range: $250K-$400K

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production. Required Technical Skills: Strong experience in flip chip packaging and assembly processes for semiconductor devices. Deep understanding of bumping technologies (solder bumps, Cu pillar, micro- bumps) and UBM/metallization systems. Experience with underfill materials, dispense techniques, flow behavior, and cure processes. Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder

What We're Looking For: We're looking for photonics packaging engineers to contribute to, and own aspects of the A-0 and A-1 packages. This role bridges the classically divided photonics and advanced packaging skillsets, and thus is an unique point in our team. Ideal Background: Experience with integrated photonics package assemblies with multiple dies Experience with integrated circuit MCM assemblies with multiple heterogeneous materials, including compound semiconductors Understanding of photonics concepts, such as mode field diameters, mode mismatch, polarization, etc. Nice to Have: Experience with large device count photonic assemblies Experience with clear underfill Experience with high density fiber attach Experience with large substrate size photonic MCM assemblies Hands-on experience with PIC design

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats. Collaborate with OSATs and material suppliers to qualify mold and underfill materials, define dispense and cure equipment requirements, and manage process transfers into production. Lead characterization of mold and underfill material properties (viscosity, gel time, cure kinetics, adhesion, CTE, modulus) and correlate material behavior to process outcomes and package reliability. Work closely with thermal mechanical modeling teams to model solder joint reliability of bump interconnects with va

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

About the job Design the high-speed signal paths that let advanced AI compute systems perform at datacentre scale. As a Signal Integrity Engineer, you will shape the electrical performance of Graphcore hardware platforms. Your work will help 112Gbps and 224Gbps SERDES, DDR and processor interfaces operate within demanding system budgets. You will develop, extract and simulate PCB structures across production systems and test boards. You will define launches, via structures, transmission lines, stack-ups and low-loss materials for future designs. This role spans simulation, lab validation and practical design influence. You will work from concept through prototype bring-up, debug, validation and support for manufacture. The team and culture You will join the Hardware Engineering team, working closely with PCB, package substrate, system architecture and supplier teams. Work moves through simulation, design review, lab evidence and practical trade-offs. You will be expected to own signal integrity decisions across complex board and package interfaces. The team values careful analysis, pace and clear communication when problems need action. Decisions are made close to the engineering detail. You will challenge designs, guide constraints and help teams reach the best performance possible. What we’re looking for · Strong experience in high-speed digital circuit development, with deep signal and power integrity knowledge · Experience with high-frequency SERDES design and validation, including tens of GHz operation · Expertise using tools such as ANSYS SIWave, HFSS, Mentor HyperLynx or similar · Ability to design BGA and connector launches, via structures and transmission lines for GHz signals · Hands-on lab experience using VNAs, high-speed oscilloscopes and signal generators · Rigorous approach to design, debug and validation, with strong ownership and communication skills While we have outlined a set of requirements, we value transferable skills and diverse experiences.

About the job Shape the power delivery foundations behind advanced AI compute systems built for real-world reliability. As a Power Integrity Engineer, you will deliver robust power integrity solutions across Graphcore silicon and system designs. Your work will help advanced compute platforms operate reliably across complex packages, PCBs and hardware systems. You will develop and analyse power delivery networks across silicon, package and PCB designs. You will use simulation, measurement and lab correlation to turn power behaviour into clear design improvements. This role gives you ownership across the full system path. You will influence decoupling strategy, stack-up decisions, bring-up debug and best practice for future platforms. The team and culture You will join the Signal and Power Integrity team within Systems Engineering Hardware Motherboard. The team works across chip, package, board and system engineering to solve problems end to end. Work moves through modelling, simulation, validation and lab evidence. You will collaborate closely with hardware teams and third parties to improve power and signal performance. You will be trusted to guide technical decisions, review peer work and speak up when designs need challenge. Ownership sits close to the engineering detail. What we’re looking for · Strong understanding of power integrity principles, including PDN design and analysis · Proficiency with PI simulation tools such as PowerDC, PowerSI, HFSS/SiWave, Simplis, Spice, ADS or similar · Experience working across chip, package or board-level design · Ability to interpret simulation results and translate them into design improvements · Knowledge of electromagnetic simulation techniques and lab measurement using equipment such as VNAs and oscilloscopes · Strong analytical skills, clear communication and the ability to work cross-functionally While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our

About the job Build the test systems that prove advanced AI hardware is ready before it reaches production. As a Test Development Engineer, you will create and maintain test systems for Graphcore’s electronic hardware platforms. Your work will support preproduction test solutions across system and board-level products. You will define test methods, specify equipment and automate systems for complex hardware. This includes high-speed serial links, high-current power supplies, slower protocols and low-level PCBA debug. This role sits close to real engineering problems. You will build deep product knowledge, improve test coverage and help transfer robust solutions into production. The team and culture You will join the Hardware Test team, embedded within Graphcore’s wider Hardware Engineering group. The team works closely with SI, mechanical, layout, package, silicon, firmware and production teams. Work moves through practical test design, lab debug, automation and clear data. You will be trusted to take ownership and develop solutions that meet real hardware needs. The team values proactive communication across Graphcore and third-party support teams. Decisions are shaped by evidence, standards knowledge and the quality of the test data. What we’re looking for · Experience developing and automating test systems for complex electronic systems · Knowledge of Ethernet and/or PCIe testing, including high-speed hardware debug · Fluency in test scripting languages, including Python and LabView · Ability to plan test work, improve coverage and communicate progress clearly · Hands-on experience with lab equipment such as oscilloscopes, BERTs and VNAs · Strong ownership, teamwork and communication skills across technical teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate. Benef

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We are looking for an experienced Mechanical Engineer with 7+ years of experience in design of IT hardware from chip/package to system levels. You’ll work alongside experts in thermal, mechanical, electrical, software, and systems engineering to support the design, analysis, and validation of mechanical and thermal systems that ensure the reliability, efficiency, and longevity of mission-critical hardware. This position requires strong analytical skills, hands-on testing experience, and the ability to work in a fast-paced, cross-disciplinary environment. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead mechanical design for AI supercomputer product in the data center application Collaborate with the cross functional team to design and optimize thermal solutions for data center hardware, including chips, power modules, and system-level cooling architectures Collaborate with cross-functional teams to integrate thermal management strategies into hardware design, from concept to mass production Design and validate mechanical systems, including chassis, enclosures, cooling systems, and high-power connections, ensuring alignment with performance and reliability standards. Perform 3D modeling, FEA, tolerance analysis, and prototyping, ensuring manufacturability and a

About the job Design the high-speed signal paths that let advanced AI compute systems perform at datacentre scale. As a Signal Integrity Engineer, you will shape the electrical performance of Graphcore hardware platforms. Your work will help 112Gbps and 224Gbps SERDES, DDR and processor interfaces operate within demanding system budgets. You will develop, extract and simulate PCB structures across production systems and test boards. You will define launches, via structures, transmission lines, stack-ups and low-loss materials for future designs. This role spans simulation, lab validation and practical design influence. You will work from concept through prototype bring-up, debug, validation and support for manufacture. The team and culture You will join the Hardware Engineering team, working closely with PCB, package substrate, system architecture and supplier teams. Work moves through simulation, design review, lab evidence and practical trade-offs. You will be expected to own signal integrity decisions across complex board and package interfaces. The team values careful analysis, pace and clear communication when problems need action. Decisions are made close to the engineering detail. You will challenge designs, guide constraints and help teams reach the best performance possible. What we’re looking for · Strong experience in high-speed digital circuit development, with deep signal and power integrity knowledge · Experience with high-frequency SERDES design and validation, including tens of GHz operation · Expertise using tools such as ANSYS SIWave, HFSS, Mentor HyperLynx or similar · Ability to design BGA and connector launches, via structures and transmission lines for GHz signals · Hands-on lab experience using VNAs, high-speed oscilloscopes and signal generators · Rigorous approach to design, debug and validation, with strong ownership and communication skills While we have outlined a set of requirements, we value transferable skills and diverse experiences.