Advanced Package Technology Development Iot Mts Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of APTD SG Technology Development Process Integrator, you will be responsible for developing advanced packaging process solution and ensure New Process, New Equipment, New Material and Path finding activities success for all adv pkg products in Micron. To lead new Technode process readiness and improving the yield, quality and reliability with process characterization and optimization and new materials, machines & technologies introduction. You will need to have understanding of Frontend Process, packaging requirements, chip package interaction, equipment understanding and process technology in the industry. The ability to enable best technology for New Technode with packaging requirements. You will also be required to drive & collaborate with cross functional teams to resolve process related problems. Ensure smooth transition from new process development, 1st qualification success to small volume production launch Development and Qualification of new packaging process, material, equipment and technology solutions to meet new Technode requirements and schedule Perform CPI NUDD, process TRA, risk mitigation execution and process recipe readiness prior Silicon arrives and ensure 1st pass rate. Qualify new process/technology/equipment/materials Technical capability Identify path finding opportunities for Micron's technology leadership with BIC time to market, continuou

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will contribute to the design and delivery of next‑generation memory products by working across circuit design, layout, and validation. You will apply simulation, modeling, and verification skills to improve

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are looking for a Director to join our Package Development & Engineering team (PDE) Your responsibilities include but are not limited to collaborating with internal and external partners to building and implement strategies aligned to organizational and business objectives by delivering high performing and cost-effective advanced packaging solutions on time with highest quality and predictable reliability performance. Other responsibilities include ensuring organizational compliance to company policies, departmental procedures, providing organizational leadership for building and implementing department strategies, processes, and policy through active participation in functional teams and projects. As the Director, PDE Advance Packaging NPI , you will provide strategic and operational leadership for the Advanced Technology PEE & PIE team within PDE. This Director-level role is responsible for overseeing the New Product I

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. This role is part of the Customer Engineering Technical Leadership function within HIG PSE. The Customer Integration Engineer will focus on technical engagement across product development, system architecture, develop, front-end and back-end process, Package Failure Analysis, Qualification, and Test. The successful candidate will have expertise in one of these subject areas and a strong appetite to learn others on the job. This position emphasizes hands-on technical problem-solving, working with multi-functional groups, and enabling successful integration of advanced HBM products into customer systems. AI adoptation and regular development and use is a must. Leveraging Artificial Intelligence is part of day to day operations Responsibilities: Apply deep technical knowledge across one or several domains such as product engineering, system engineering, building, front-end/back-end process, PFA, qualification, or test. Support integration of customer requirements into internal design and manufacturing processes. Participate in technical reviews, debug sessions, and failure analysis activities. Work closely with internal teams across build, product engineering, and manufacturing to resolve technical challenges. Assist in yield improvement and qualification efforts tied to customer programs. Minimum Qualifications: Bachelor’s or Master

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. This role is part of the Customer Engineering Technical Leadership function within HIG PSE. The Customer Integration Engineer will focus on technical engagement across product development, system architecture, develop, front-end and back-end process, Package Failure Analysis, Qualification, and Test. The successful candidate will have expertise in one of these subject areas and a strong appetite to learn others on the job. This position emphasizes hands-on technical problem-solving, working with multi-functional groups, and enabling successful integration of advanced HBM products into customer systems. Responsibilities: Apply deep technical knowledge across one or several domains such as product engineering, system engineering, building, front-end/back-end process, PFA, qualification, or test. Support integration of customer requirements into internal design and manufacturing processes. Participate in technical reviews, debug sessions, and failure analysis activities. Work closely with internal teams across build, product engineering, and manufacturing to resolve technical challenges. Assist in yield improvement and qualification efforts tied to customer programs. Minimum Qualifications: Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering, Mechanical Engineering, Materials Science, or related technical field. Hands-on experience in one or more areas: product development, sys

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments. This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs. Responsibilities: Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling. Build reusable, a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG) and develops industry-leading High Bandwidth Memory (HBM) solutions for next-generation AI and high-performance computing systems. Micron is hiring an experienced MTS - Thermal Simulation Engineer! You would provide technical leadership in advanced thermal and thermo-mechanical modeling for next-generation High Bandwidth Memory (HBM) products. This role will define simulation strategy, solve complex thermal challenges across 2.5D/3D semiconductor packaging systems, drive physics-based model development and silicon correlation, and influence product, package, material, and process decisions across teams . Key Responsibilities Lead the development of high-fidelity thermal and thermo-mechanical models for HBM packages, including die, interconnects, bonding interfaces, and system-level integration. Define and implement multiphysics simulation strategies encompassing thermal, structural, and coupled analyses to evaluate performance, identify risks, and guide architecture and design decisions. Provide deep technical analysis of thermal transport, heat flux distribution, and thermo-mechanical behavior across complex stacked memory architectures. Lead simulation-to-silicon correlation with characterization and test teams, establish model validation criteria, and drive closure of gaps between prediction and measured behavior. Assess material prop

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As MSH PDE Yield Enhancement (YE) Lead Engineer within Package Development Engineering (PDE), you will lead a team of YE Engineers responsible for yield performance, excursion management, and yield stabilization across High Bandwidth Memory (HBM) New Product Introduction (NPI) . This role is accountable for ensuring predictable yield ramps , fast learning closure , and robust manufacturing readiness for advanced HBM technologies. You will provide people leadership, technical direction, and execution governance , partnering closely with Process Integration (PI), MRDA, Process Engineering, Assembly/Test Manufacturing, Quality, and Program Leadership to protect schedule, yield, and customer commitments. Job Responsibilities People & Team Leadership Build, lead, and develop a high‑performing MSH PDE YE team Set clear expectations on yield ownership, execution discipline, and escalation behavior Coach engineers on technical rigor, structured problem solving, and stakeholder communication Drive individual development plans, succession planning, and technical depth within the YE team Ensure sustainable on‑call / coverage models for critical NPI and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role Overview The ASIC Test Engineer is responsible for test program development, silicon validation, yield analysis, and production test optimization for advanced ASIC/SSD controller products. This role supports both NPI and HVM phases, driving fast ramp, robust quality, and cost-effective test solutions across wafer sort and final test. Key Responsibilities Develop and debug ATE test programs for wafer sort and final test (probe to package) to support silicon bring-up and production ramp. Drive yield analysis, failure characterization, and root cause investigation to accelerate yield improvement and ensure product quality. Collaborate with design, product engineering, reliability, and OSAT teams to resolve test and silicon issues across the product lifecycle. Optimize test coverage, test time (TTR), and cost through test content development, guardband tuning, and screening strategy improvements. Support hardware bring-up including probe cards, load boards, and tester configurations to ensure stable manufacturing operations. Enable efficient NPI execution by developing scalable test solutions and improving cycle time from bring-up to HVM. AI/Advanced Data Capability Apply AI/ML and data-driven methodologies to enhance yield analysis, anomaly detection, and failure classification. Leverage AI-assisted tools (e.g., code generation, debug automation, data analytics platforms) to improve engineering productivity and debug cycle time.<br

Position: Robot Operator (Glass Cleaning) Location: Bangalore Job Type: Full-Time Department: Operations Role Overview This role involves operating advanced robotic window-cleaning systems at residential, retail, office, and commercial locations. Candidates should be comfortable handling technology, performing basic troubleshooting, ensuring service quality, and interacting professionally with customers. Key Responsibilities • Operate robotic glass and window-cleaning equipment with proper safety procedures. • Perform routine maintenance, inspections, and basic troubleshooting. • Carry out manual touch-up cleaning whenever required. • Ensure high-quality service delivery and customer satisfaction. • Record job updates, customer feedback, and service issues through CRM systems. • Support customer engagement and identify opportunities for additional services. Required Skills & Qualifications • Tech-savvy with the ability to learn robotic operations and mobile applications quickly. • Basic mechanical aptitude and troubleshooting skills. • Good communication skills in English, Hindi, and Kannada. • Physically fit to handle equipment and perform occasional manual cleaning. • Customer-friendly attitude with strong service orientation. • Two-wheeler preferred for local travel (fuel allowance provided). • Prior experience in cleaning services, field operations, appliances, maintenance, or home services is an advantage. What We Offer • Competitive salary package. • Incentives on upselling and cross-selling opportunities. • Performance-based bonuses. • Professional training on robot operations, safety, and customer handling. • Uniforms, equipment, and consumables provided by the company. • Career growth opportunities into Senior Operator, Supervisor, and Technician roles. • Dynamic start-up environment with long-term career development. About the Company A Bangalore-based Robot-as-a-Service (RaaS) start-up delivering innovative automated cleaning solutions across B2B and B2C

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of the Heterogeneous Integration Group within Technology and Products, where we build High Bandwidth Memory solutions that power AI and ML platforms. Our team works at the edge of what’s possible, stacking and integrating advanced silicon technologies to deliver industry‑leading bandwidth, density, and power efficiency. We move fast, solve hard problems, and set technical direction others follow! This role sits at the center of next‑generation HBM development. As a senior SI/PI technical authority, you will shape system‑level decisions that directly impact performance, reliability, and scalability across multiple product generations. If you enjoy deep technical ownership, complex problem solving, and influencing architecture from concept to sign‑off, this role offers both challenge and impact. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Lead signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency‑ and time‑domain evaluation Define and drive power delivery architecture, impedance targets, and transient analysis Perform electromagnetic extraction and modeling across PCB, package, and interposer designs Establish SI/PI standards, methodologies, and sign‑off criteria for HBM system designs Provide clear technical direction in ambiguous or incomplete design environments Minimum Qualifications: 7 years of experience in

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead system signal integrity (SI) design for AI supercomputer product in the data center application. Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity Perform simulation and modeling to identify and troubleshoot signal integrity issues Lead system interconnect design, bring up and qualification As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings. You might thrive in this role if you: Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications Have a strong bias toward action, and won’t take no for an answer. Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level Have ex

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a PDE MRDA KEG Engineer / Senior Engineer , you will be responsible for developing, qualifying, deploying, and sustaining advanced defect inspection and metrology solutions that support New Product Introduction (NPI), HBM technology ramps, and High Volume Manufacturing (HVM). You will drive inspection capability readiness, equipment performance improvement, and defectivity reduction through close collaboration with cross functional team. The role requires strong expertise in semiconductor manufacturing, defect inspection technologies, data analytics, equipment qualification, and cross-functional problem solving to enable industry-leading process control and yield performance. Inspection Technology & Equipment Ownership Manage advanced inspection and metrology platforms throughout package development and manufacturing. Develop technology roadmaps and capability strategies to meet future packaging requirements. Drive equipment lifecycle management, capacity planning, and technology insertion activities. Equipment Qualification & Deployment Lead tool installation, qualification (TIQ), release, and production readiness activities. Establish equipment acceptance criteria, qualification methodologies, and deployment pla

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and