Advanced Packaging Engineer Jobs

About the Role You will contribute to and own aspects of the Volantis A-0 and A-1 package. We are interested in both people with package design as well as package process development backgrounds Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more. We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP. This creates both unique challenges and opportunities. The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. What We Look For Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. What works for 5x reticle platforms may not work for 56x reticle platforms Design or process development of complex packages Nice to Have: Experience with heterogeneous material assemblies Experience with high-TDP packages Experience with compound semiconductor assemblies Experience with co-packaged optics Ability to work with architects to co-design system architecture and package design Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc Experience with flip-chip integration, especially mass reflow, TCB & LAB Experience with large scale (>50x50mm) substrates Compensation Package:

What We're Looking For: We're looking for photonics packaging engineers to contribute to, and own aspects of the A-0 and A-1 packages. This role bridges the classically divided photonics and advanced packaging skillsets, and thus is an unique point in our team. Ideal Background: Experience with integrated photonics package assemblies with multiple dies Experience with integrated circuit MCM assemblies with multiple heterogeneous materials, including compound semiconductors Understanding of photonics concepts, such as mode field diameters, mode mismatch, polarization, etc. Nice to Have: Experience with large device count photonic assemblies Experience with clear underfill Experience with high density fiber attach Experience with large substrate size photonic MCM assemblies Hands-on experience with PIC design

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust pa

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats.

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mi

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reli

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary: We are currently experiencing a ground-breaking period in artificial intelligence (AI), where AI is anticipated to become an integral component of daily life. This proliferation is being fueled by advances in memory and compute technologies. High bandwidth memory (HBM) is at the forefront of these innovations. Micron’s Advanced Packaging Technology Development (APTD) is responsible to deliver package development for high performance memory products and transfer to manufacturing . We are looking f

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary: We are currently experiencing a ground-breaking period in artificial intelligence (AI), where AI is anticipated to become an integral component of daily life. This proliferation is being fueled by advances in memory and compute technologies. High bandwidth memory (HBM) is at the forefront of these innovations. Micron’s Advanced Packaging Technology Development (APTD) is responsible to deliver package development for high performance memory products and transfer to manufacturing . We

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering — Fab 10A, Singapore. Apply via Workday.

Engineer, APTD CEM - Advanced Packaging Equipment Engineering — Fab 10A, Singapore. Apply via Workday.

Engineer, APTD CEM - Advanced Packaging Integration Engineering — Fab 10A, Singapore. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary: As an Advanced Packaging Characterization Engineer within Advanced Packaging Technology Development (APTD), your responsibilities include but are not limited to providing package development characterization and failure analysis support for development test vehicles, qualifications, customer returns, new product introduction, and general test failures. You are the domain expert on advanced packaging characterization methodology and responsible for establishing relevant analysis methods needed to support technology development. You will also have a thorough understanding of product package assembly and process flow, to work with Process Integration, Process Dev

ADVANCED PACKAGING TD - SR ENGINEER PROCESS INTEGRATION — Taichung - Fab 16, Taiwan. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Specific Responsibilities: 1. Drive HBM process development and yield improvement in FILMs process. 2. Assist advanced package technology (chip stacking, 2.5D or 3D) research and development 4. Support project on-site execution and make decisions as technical consultant 5. Troubleshoot a variety of complex problems. Perform root cause analysis and resolve process engineering issues 6. Generate internal and external documentation for presentations and technical reports Technology Development: 1. Understand department and organizational goals and objectives to ensure daily tasks align with Technology Development needs. 2. Project engagement with cross-team interaction, providing expert contribution in materials characterization. 3. Coordinate mechanical characterization for advanced packaging development efforts globally including US, Japan, and Singapore site. 4. Provide recommendations for test structure and test vehicle design for material property evaluation. 5

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Specific Responsibilities: 1. Drive HBM process development and yield improvement in WSS process. 2. Assist advanced package technology (chip stacking, 2.5D or 3D) research and development 4. Support project on-site execution and make decisions as technical consultant 5. Troubleshoot a variety of complex problems. Perform root cause analysis and resolve process engineering issues 6. Generate internal and external documentation for presentations and technical reports Technology Development: 1. Understand department and organizational goals and objectives to ensure daily tasks align with Technology Development needs. 2. Project engagement with cross-team interaction, providing expert contribution in materials characterization. 3. Coordinate mechanical characterization for advanced packaging development efforts globally including US, Japan, and Singapore site. 4. Provide recommendations for test structure and test vehicle design for material property evaluation. 5.