Analog Circuit Design Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Introduction At Micron's High Bandwidth Memory (HBM) team, we develop advanced memory solutions that enable next-generation artificial intelligence and high-performance computing applications. We collaborate across global engineering teams to deliver innovative semiconductor technologies that help transform how the world uses information. Join us and help build the future of memory innovation! Position Overview As a Layout Build Engineer within the HBM organization in Guadalajara, Mexico, you will develop and integrate analog, mixed-signal, and custom digital layouts for advanced memory solutions. You will support physical build implementation, verification, and project execution while collaborating with global engineering teams to deliver high-quality layouts on schedule. This role contributes directly to AI-enabled and high-performance computing products through efficient and reliable layout development. Responsibilities Develop analog, mixed-signal, custom digital block layouts, and support full-chip integration activities. Perform layout verification activities, including Build Rule Check (DRC), Layout Versus Schematic (LVS), antenna checks, quality reviews, and documentation. Deliver block-level layout builds on schedule while meeting established quality requirements. Lead layout planning, area and schedule estimation, task delegation, and execution across multiple concurrent projects. Work together with international engineering groups to

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Principal Layout Designer in the Next-generation HBM Architecture Team , you will drive layout for 3D-stacked, high-performance memories. Apply your knowledge to deliver high-quality layout designs across analog and/or mixed-signal domains in collaboration with peer architecture, design, and packaging teams. Implement layout designs for early architecture concepts to demonstrate feasibility and identify optimizations. Responsibilities: Design layouts for critical analog and mixed-signal blocks. Drive exploratory layout process for next-generation architectures, including floorplanning, placement, and routing. Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration. Minimum Qualifications: Hands-on layout experience with critical analog blocks and full designs. Experience with Cadence VLE/VXL and Mentor Graphics Calibre DR

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our team is at the forefront of developing next-generation memory and AI computing platforms. We are core contributors to the design, validation, and mass production of advanced systems using emerging memory technologies, ASICs, FPGAs, high-speed digital interfaces, mixed-signal and analog circuitry, and complex power delivery architectures! We are seeking a highly experienced Mechanical & Thermal Engineer to provide technical leadership and drive the mechanical and thermal architecture of ground breaking hardware platforms. This role offers the opportunity to influence product strategy, lead critical engineering decisions, and collaborate across global multidisciplinary teams to enable world-class computing solutions. The ideal candidate brings deep expertise in thermal, mechanical, and heat mitigation solutions for memory product. They demonstrate strong analytical and problem-solving skills. They have a proven record of delivering products from concept through high-volume manufacturing! Performs design and development engineering assignments related to hardware products and systems including development of new products or updates to existing products. Work may encompass one or more areas of engineering including electronic design, mechanical design, or other related fields. Duties may include research, evaluation, development, and application of new processes and methods into products. May be responsible for establishing and conducting testing routines, developing or implementing project plans, budgets, and schedules, and documentation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Summary: As a Design Verification Engineer Intern at Micron, you will collaborate with highly innovative design and verification teams to support the development of advanced DRAM and emerging memory technologies. This role offers hands-on exposure to high-density memory products, complex verification methodologies, automation tools, and industry-leading semiconductor design practices. You will work within a global engineering environment while learning from experienced engineers and contributing to world-class memory solutions. Responsibilities Support verification activities while developing an understanding of chip-level and block-level functionality for advanced memory products. Assist in developing and maintaining digital and analog verification environments for DRAM technologies. Create test patterns, execute regressions, and help improve functional coverage of memory features and architectures. Analyze verification failures, support debugging efforts, and collaborate with engineers to identify root causes. Participate in automation, scripting, AI-assisted engineering solutions, and verification flow improvements while collaborating with global teams. Minimum Qualifications Currently pursuing the final year of a Bachelor's degree or a Master's degree in Electronics Engineering, Electrical Engineering, or a related field, with enrollment in an accredited university program. Basic understanding of digital logic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Leading all aspects of and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to improve the design quality Driving innovation into the future Memory generations within a dynamic work environment Design Planning & Top-Level Integration Perform top-level virtual flat placement to explore partitioning options and validate hierarchy quality before commit. Implement top-level global routing to derive congestion, timing, and pin-feasibility signals that drive planning decisions. Own partition creation : block shaping, abutment, channel/keep-out definition, and power-domain planning. Drive pin optimization / pin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ​Directs and Manage team activities related to the analysis, design, programming, debugging, troubleshooting, and modification of software for firmware (IC embedded code) applications. Oversees programming activities involving analog and digital hardware and software operating systems. May have responsibility for the programming of assembly language, machine language and high level languages, including but not limited to C and C++. Selects, develops, and evaluates personnel to ensure the efficient operation of the function. 12+ Years in Embedded Firmware - Storage/SSD would be a strong plus. Strong firmware design and debug experience using assembly and C programming. Knowledge of SSD flash translation layer, wear leveling, garbage collection, etc. Knowledge of mass storage interfaces such as SAS, SATA, NVMe (optional but strong plus). Knowledge of configuring and debugging issues from the usage of register settings of ASICs in an SoC and embedded firmware dev environment High level of skill in problem recreation and trapping, and in identifying performance critical algorithms for optimization - AI Supported Strong skill in ARM development tools and IDE Ability to scope and estimate development effort. Ability to work and communicate effectively in a team, able to multitask effectively in fast-paced environment. Experience in test equipment such as oscilloscopes and logic/bus analyzers (good to have). Experience

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution. Drive layout implementation of complex analog, mixed-signal, memory, and high-speed interface designs. Own DRC, LVS, ERC, EMIR, reliability, and manufacturability closure. Define and scale layout methodologies, best practices, and execution frameworks. Leverage Artificial Intelligence, Machine Learning, and Agentic AI to improve layout productivity, design quality, automation, and faster decision-making. Drive automation initiatives using AI-assisted design, verification, debugging, and knowledge management solutions. Lead cross-functional and global teams, mentor engineers, and drive technical excellence. Qualifications B. Tech /M. Tech in Electrical Engineering, Electronics, VLSI, or related field. 15&#43; years of hands-on custom layout experience. Proven success leading full-chip programs from concept through silicon tape-out. Deep expertise in: Analog & Mixed-Signal Layout Memory & High-Speed Interface Layout Full-Chip Floor planning & Integration Signal Integrity, Power Integrity, EM/IR Physical Verification & Signoff Advanced Node Technologies (FinFET/GAA) Strong proficiency with Cadence Virtuoso, Calibre, StarRC, Totem, and related EDA tools. Proven experience leveraging <

What You'll Do Physical scientist/engineer to take responsibility for testing and validation of novel hardware systems What We're Looking For Hands-on laboratory experience and the ability to work independently Familiarity with test and measurement equipment including: oscilloscopes, lock-in amplifiers, spectrum analyzers, PID controllers, etc. Proven diagnostic and troubleshooting skills, coupled with the drive to understand experimental results fully before proceeding Diligent record-keeping habits and facility with Python/Matlab/equivalent for data analysis and visualization Ability to work on-site (up to five days/week) in the San Francisco Bay Area Given the nature of the work, U.S. citizenship is required. Useful Experience Background in experimental physics, particularly in quantum or optical measurements Hands-on EE design and manufacturing experience: analog and digital electronics, board layout, soldering, etc. Excellent data presentation skills A desire to learn new skills outside your current area of expertise Proficiency using the latest AI tools to accelerate workflow

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's ASIC Logic Design team develops next-generation ASICs and controller IP that enable industry-leading memory solutions. Working across advanced process technologies, the team collaborates with architecture, analog, verification, physical design, and validation engineers to deliver high-performance, production-ready silicon for future DRAM products. As an ASIC Digital Design Engineer, you will contribute to the design and development of RTL for next-generation DRAM memory controllers and subsystems. You will work in a collaborative engineering environment supporting design implementation, simulation, validation, and chip bring-up activities while leveraging AI-enabled tools to improve productivity and design quality. Responsibilities Design and develop RTL for DRAM memory controllers and subsystem components using SystemVerilog. Collaborate with analog, verification, physical design, validation, and other cross-functional teams to support successful product development. Develop and validate HDL models, support simulation and co-simulation activities, and analyze design functionality and performance. Support chip bring-up, debugging, and validation activities to identify and resolve design issues. Use scripting, automation, and AI-enabled tools to improve design workflows, productivity, and engineering efficiency. Minimum Qualifications 0-2 years of relevant experience through intern

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions for AI, machine learning, and high-performance computing applications. We are seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. This role focuses on PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks that enable industry-leading bandwidth, power efficiency, and robustness. The successful candidate will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture teams to define architectural requirements, drive technology innovation, and ensure successful translation from concept to silicon. As a technical leader, you will influence future HBM roadmap decisions, develop engineering methodologies, and mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design. Key Responsibilities Define and drive next-generation HBM PHY and IO architecture , balancing performance, power, area, reliability, and manufacturability requirements. Architect high-performance transmit and receive paths , including clocking, signaling, equalization, timing alignment, and interface optimization. Define and optimize analog calibration architectures , including impedance calibration, reference v

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribu te to the development of new product opportunities by assisting with the overall design, layout, and optimization of DRAM Memory array / Peripheral Logic/Analog circuits Actively leverage AI ‑ based tools, agentic workflows, and automation frameworks to : Accelerate schematic optimization and design ‑ space exploration Assist in parasitic analysis, sensitivity studies, and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribu te to the development of new product opportunities by assisting with the overall design, layout, and optimization of DRAM Memory array / Peripheral Logic/Analog circuits Actively leverage AI ‑ based tools, agentic workflows, and automation frameworks to : Accelerate schematic optimization and design ‑ space exploration Assist in parasitic analysis, sensitivity studies, and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom<spa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modelling. P

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global Defense Line (DL) matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment for DL signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modelling. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience or know-how in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modellin