Analog Circuit Design Engineer Jobs

Job Details: Job Description: We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance. Key Responsibilities: • Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates). • Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools. • Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules. • Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives. • Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions. • Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts. Qualifications: Required Skills: • Experience with PERC rule development (preferably using Calibre PERC). • Knowledge of ESD, latch-up and reliability verification. • Familiarity with SVRF, TVF, Python or Tcl scripting. • Strong debugging and problem-solving skills. • Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable. • Experience with advanced technology nodes is an advantage. • Team player and be able to work with globa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Guide team members in their execution of Sub block-level layouts & review their work Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products. Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA). Technical Expertise : Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Drive project planning and execution , including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs. Ensure timely delivery with quality , responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations. Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits. Lead and mentor the layout team , guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development. Drive innovation and productivity improvements , including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality. <li

What We’re Looking For: We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort. Ideal Candidates: Ideal candidates will have: Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them Experience both with in-house and outsourced physical design flows Nice to Have: Experience with physical design process for multi-die/multi-chiplet/MCM designs Experience with physical design process for reticle-max or near reticle max designs Experience with very high power density chips Experience with the physical design process for AI chips Experience with the physical design process of analog and mixed signal blocks and macros

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Anthropic runs some of the largest AI training and inference workloads in the world, across multiple hardware platforms. We work from the chip level up with our silicon partners, and we are now deepening that investment by building a custom silicon team. You will be one of a small number of people covering a large surface. We are opening searches across the key domains below, and we are interested in candidates whose center of gravity sits in any of them: Front-end design Pre-silicon verification Physical design Design for test Analog and mixed-signal Technology and foundry CAD and design infrastructure Packaging, signal integrity, and power integrity This is a role for someone who has shipped silicon, has a realistic relationship with schedules, and is comfortable making consequential calls without a large organization behind them. Key responsibilities Take part in end to end activities for the program: strategy, specification, execution and the technical bar. Write the specifications and interface definitions that others design against and keep them coherent as the architecture converges Make and own directional calls: technology and IP selection, where we build versus buy versus license, and where we take design authority versus rely on partners Build and share AI-assisted approaches to the code-like parts of your domain, and help the team learn what Claude can genuinely accelerate Contribute to the architecture and micro-architecture discussion from your domain's perspective, including the tradeoffs your area imposes on the rest of the chip Partner with Anthropic's inference, performance, kernels, and infrastr

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Responsibilities Lead and develop a Custom layout team for Micron’s global NAND layout needs. Lead the development of analog and custom layout to achieve project schedules and achievements. Offer leadership in developing the team's technical capabilities and fostering a positive, inclusive culture. Successfully collaborating with engineering teams across India, US, Japan, and Italy to ensure the layout project’s completion. Coordinate and prioritize logistics and resources across multiple projects. Coordinate with TD, Design, CAD, and layout teams to ensure timely, quality delivery. Drive innovation for future memory generations in a dynamic work environment. Lead all aspects of team performance and growth. Hiring and retention management. As part of Micron's core NAND leadership in India, help drive the success of NAND operations. Proficiency in Cadence VLE/VXL and Calibre DRC/LVS is required. Demonstrates strong motivation and enthusiasm, maintains attention to detail, and applies a systematic and methodical approach in IC layout design & planning. Prior experience with NAND or any other non-volatile memory is preferred, though it is not mandatory. Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies Leverage AI tools to automate the tools and workflow Applying Artificial Intellige

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The qualifications and skills for this position include, but are not limited to: Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering with 7&#43; years of proven experience in Test Engineering role. Excellent programming skills for writing and debugging ATE test programs and test-related hardware development. Proficiency with Advantest V93K ATE platforms and/or other logic device ATE testers is preferred. Proficiency in programming with C/C&#43;&#43; and/or JAVA is required. Solid understanding of testing for CMOS SoCs. Prefer candidates with exceptional digital, analog, and MXS test programming and debug experience. Familiar with testing IP blocks such as PLL, efuse, DDR. Expertise in test strategy development, test plan definition, DFT pattern implementation (ATPG SCAN, TDF, MemBIST and repair, BSACAN, JTAG/IEEE1500, and Functional Patterns). Expertise in ATE architecture and test hardware design and debugging, schematic capture, and PCB layout. ATE test vector conversion tools like VTRAN and proficiency in debugging issues during development or high volume production. Knowledge of semiconductor manufacturing process. Knowledge of accurate and effective use of lab test equipment (i.e., oscilloscope, logic analyzer, etc.). Experience with data analysis software in support of c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior/Staff Engineer, NAND Product Development in Non-Volatile Engineering (NVE) group at Micron Technology, Inc., you will be responsible for test flow development and testing strategies with emphasis on Test Chips for Micron’s pioneering 3D NAND memory. You will be collaborating with multiple teams like Test Solutions Engineering on test code development, Design Engineering on testmode implementation, and validating and debugging testmodes and test results via simulation and post silicon validation of the tests. Provide critical test solutions that will be used to screen the quality and reliability failures on Micron’s NAND products. Responsibilities: NAND Testchip test flow development and validation Run pre si Verilog (Digital) and Analog design simulations to verify testmodes. Define and improve post si testing methods to address new experimental designs, process or debug issues on devices manufactured at Micron’s R&D and Fab10 Manufacturing facilities Perform device characterization and electrical failure analysis (EFA) Collaborate with Test Solutions Engineering on test code development. Collaborate with Design Engineering on testmode implementation, pre si verification and post si validation of testmodes. Collaborate with Process Integration, yield engineering to improve overall die yield and meet the critical turning points planned for the Testchip. Leverage AI tools to automate the tools and workflow</

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s DPG-IPDEV Team in Bangalore, India. DPG-IPDEV team is responsible for developing world-class analog and mixed signal IPs used in every cutting edge DRAM chip produced in Micron . As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for timely delivery of block-level layouts with acceptable quality. • Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project sche

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products. Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA). Technical Expertise : Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Drive project planning and execution , including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs. Ensure timely delivery with quality , responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations. Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits. Lead and mentor the layout team , guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development. Drive innovation and productivity improvements , including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality. <li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration Ensure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications. Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation. Collaborate with global engineering teams to ensure successful execution and integration of layout projects. Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development. Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects. Contribute actively to project management and cross-functional coordination. Proven experience in IC layout design with a systematic and methodical approach. Strong attention to detail and a passion for high-quality design. Excellent communication and collaboration

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality Driving innovation into the future Memory generations within a dynamic work environment About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Guide team members in their execution of Sub block-level layouts & review their work Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performa