Architect Memory Subsystem Jobs

What We’re Looking For: We’re looking for memory subsystem architects to contribute and own aspects of the memory subsystem for the largest and highest bandwidth memory system ever built to date. This includes the distributed memory fabric, memory controllers, interface with the XPUs/compute complex, etc. Ideal Candidates: Ideal candidates will have: Deep knowledge and hands-on experience in the design and implementation of memory sub-systems Understand LLM inference workloads and what the impact of that for the memory subsystem is Understand the benefits and limitations of memory tiering for various workloads Nice to Have: Experience with CXL and other memory pooling protocols Experience with design and implementation of memory controllers Experience with processing in memory and other “unique” memory subsystem projects and efforts

Job Details: Job Description: About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments. What You’ll Do Key responsibilities will include but not limited to: Cache Hierarchy and Coherency Architecture 1. Define and evolve multi-level cache hierarchy (private/shared caches, system-leve

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) <li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues acros

What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations. Ideal Background: An ideal candidate will have: Experience with full ownership of the specs and drove implementation for at least one SoC/die A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks Nice to Have: Experience with multi-die/multi-chiplet/MCM designs Experience with reticle-max/large-die SoC architecture Understanding of levers available for improving PPA Track record of very high speed A0 silicon delivery

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a System Architect in Advanced System Architecture Group at Micron Semiconductor Products, Inc., you will work with the memory industry's leading architecture team on new concepts that will craft the future of electronic systems around AI, servers, and mobile systems. You should be able leverage Artificial Intelligence for driving the processes and build next gen solutions with AI Supported frameworks. Your Responsibilities Will Include, But Are Not Limited To Delivering architectures and innovative solutions to optimize power and performance of next-generation memory and storage subsystems. Working with design and system architecture teams to identify key system requirements, seek the current bottlenecks and propose novel solutions for a wide range of applications. These activities will entail: Performing system-level simulations of innovative architectures to compare with existing design paradigms, using both open and closed-loop system performance analysis. Developing mode

About the job Shape the SoC architecture behind Graphcore's next generation of AI acceleration platforms. Graphcore is expanding its Silicon Architecture Team in Bristol to deliver complex AI compute platforms. As a SoC Architect, you will define how critical subsystems are specified, modelled and integrated. You will turn product requirements into architecture choices across interfaces, interconnect, memory and platform behaviour. Your work will guide implementation, validation and trade-offs across multiple chip programmes. You will work with processor, SoC and system architects, plus design, verification, hardware and software teams. Together, you will evaluate IP, resolve integration questions and support silicon bring-up where needed. This is a rare chance to influence real AI silicon while Graphcore scales its contribution to SoftBank Group's AI ecosystem. The team and culture The team owns SoC architecture, subsystem modelling and system-level trade-offs across future AI acceleration platforms. Work moves from requirements to specifications, models, reviews and guidance for implementation teams. People here are expected to take responsibility early and keep decisions moving. You will speak directly with adjacent teams to clarify constraints, challenge assumptions and close open questions. Decisions are made through technical evidence, clear specifications and direct cross-functional discussion. The team values people who think big, act fast and spea

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products. You will work with design, verification, firmware, and system teams to determine emulation needs and opportunities. You will drive the development of hardware emulation ecosystem including procurement of hardware emulation platforms, creation of emulation testbenches and transactors, and development of emulation friendly verification IP. You will be responsible for proactively developing emulation capabilities to meet the needs of current and future products. You will also lead the effort to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Responsibilities will include, but are not limited to: Develop and maintain hardware emulation environments for complex SoCs and subsystems. Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions that enable advanced AI, high-performance computing, data center, and networking applications. Our team collaborates across architecture, RTL design, verification, physical design, firmware, and product engineering to deliver innovative memory-centric SoC solutions that meet demanding power, performance, area, quality, and schedule objectives. As an HBM SoC Design Engineer/Architect, you will contribute to the design, integration, and validation of advanced HBM logic die and memory-centric SoCs. Working alongside experienced engineers, you will apply knowledge gained through academic coursework, research, internships, and engineering projects to solve real-world semiconductor design challenges. This role offers opportunities to develop expertise in digital design, ASIC development, HBM architecture, and AI-enabled engineering methodologies that i

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery. In this role you will: Define the architecture and technical roadmap for custom SoCs targeted for edge applications. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments. Collaborate with internal hardware, software, systems, and product teams to align architecture with platfo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal HBM RTL Designer, you will serve as a technical leader driving the front‑end digital design of next‑generation High Bandwidth Memory (HBM) products. This role requires deep expertise in RTL architecture, build methodology, and multi-functional technical leadership. You will own complex design blocks end‑to‑end—from architectural definition through production‑quality implementation—while mentoring engineers, influencing design strategy, and ensuring world‑class design execution. Responsibilities: Define, architect, and lead the development of advanced RTL blocks for HBM subsystems, ensuring alignment with product requirements and architectural goals. Own end‑to‑end front‑end design, including micro‑architecture, RTL development, simulation strategy, and design quality. Drive technical decisions across circuit development, synthesis, constraints, and physical‑design integration, ensuring timing, power, and area compliance. Champion design methodologies, develop reusable frameworks, and improve RTL design flo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. HBM Design Architecture — Principal Engineer Role Overview We are seeking a highly motivated HBM Design Architecture Engineer (Principal Engineer) to drive exploration and definition of next‑generation AI memory and system environments. In this role, you will analyze emerging infrastructure trends, build performance models, and develop/extend tooling that informs HBM architecture decisions and system‑level trade‑offs. You will work closely with architects and senior engineers across DTPCO, Design, and Product/System teams to translate AI workload requirements into actionable memory subsystem and architectural intercept strategies. Key Responsibilities You will own and contribute to projects such as: Research and synthesize emerging trends in compute, networking, and storage infrastructure to anticipate how future AI systems will evolve. Lead HBM architecture analysis by defining bandwidth/latency targets, identifying constraints, and tra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About the Team At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team develops future High-Bandwidth Memory (HBM) architectures, PHY design methodologies, and automation solutions that enable next-generation AI, high-performance computing, networking, and data center applications. The team works closely with Architecture, Design Engineering, Verification, Product Engineering, and external partners to advance memory technologies while improving design quality, productivity, and development efficiency. Position Overview As a Senior or Graduate Engineering Intern, you will collaborate with experienced HBM architects and engineers to support the development of digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next-generation HBM PHY and IO subsystems. This role offers hands-on experience in digital design, verifi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Memory Systems Engineering team and contribute to the development of premier digital and mixed-signal foundations for our high-bandwidth memory (HBM) products. This position offers an outstanding chance to work intimately with multiple engineering areas, guaranteeing the smooth integration and implementation of HBM base die. Join a motivated team committed to delivering robust first-pass silicon that meets our strict bandwidth, latency, power, and reliability objectives! Responsibilities Assist in defining and carrying out digital micro-architecture for HBM base-die subsystems, covering channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance counters, and reliability features. Translate system requirements into timing, power, and area considerations by partnering with physical layer and system architects, and help maintain interface specifications for bus protocols, clock-domain crossings, and reset strategies. Implement and integrate sy

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets. In this role, y ou'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows. Responsibilities Define and implement digital micro-architec