Architect Memory Subsystem Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role passionate about RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer

About the Team OpenAI’s Hardware organization develops system and infrastructure solutions designed for the unique demands of advanced AI workloads. We work closely with architecture, infrastructure, and vendor teams to evaluate system performance and guide critical design decisions. Our team focuses on building and applying performance modeling frameworks to understand system behavior, quantify tradeoffs, and inform next-generation infrastructure design. About the Role We are seeking Performance Modeling Engineers to develop and apply modeling tools that evaluate AI system performance and inform architectural decisions. In this role, you will work closely with the Performance Modeling Lead and partner teams to analyze system behavior, run simulations or analytical models, and help quantify tradeoffs across compute, memory, networking, and storage. You will contribute to building modeling frameworks and applying them to real-world questions that impact system design and vendor decisions. This role is well-suited for engineers with strong software or modeling backgrounds who are interested in developing deeper expertise in system architecture and AI infrastructure. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Develop and maintain performance modeling tools and frameworks. Build models to evaluate system behavior across: compute, memory, and interconnect subsystems distributed system scaling and bottlenecks. Run simulations and analytical models to support architectural tradeoff analysis. Collaborate with performance modeling lead and system architects to answer forward-looking design questions. Analyze and interpret modeling outputs, translating results into actionable insights. Validate models against real system measurements and workload behavior. Contribute to improving modeling fidelity, usability, and scalability. Qualifications Strong software engineeri

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Global Sales organization at Micron sits at the center of innovation and customer impact. We work directly with the world’s most advanced cloud and enterprise customers, helping them solve real system-level challenges using cutting-edge memory and storage technologies. If you enjoy shaping strategy, influencing roadmaps, and working across cultures and disciplines, this team offers a unique opportunity to make a global impact. As a Staff Cloud Solutions Architect, you play a critical role in building trusted technical partnerships with key customers and ecosystem partners. You will lead account-level technology strategy, guide solution design, and help customers optimize system architectures across Micron’s portfolio. This is a highly visible role that blends deep technical expertise, customer engagement, and cross-functional leadership! Responsibilities: Lead technology strategy for assigned cloud and enterprise accounts in partnership with Sales and field teams Build trusted technical relationships with customers and ecosystem partners by aligning Micron solutions to system-level challenges Provide system and solution-level guidance, including trade-offs across performance, cost, and compatibility Develop and share reusable solution designs and best practices across the sales organization Influence product and solutions roadmaps by representing the voice of the customer across busines

Staff Cloud Solutions Architect (Memory & Storage) — Munich (Leopold), Germany. Apply via Workday.

NVIDIA is seeking a world-class computer architect to contribute to the development of future high-performance computing systems, with a focus on enhancing the power-constrained performance of the hardware. Ideal candidates will have a strong track record of understanding and analyzing memory systems architecture to improve performance per watt (perf/W) and performance per millimeter (perf/mm). A broad perspective across the field of computer architecture and depth in the area of power, performance, and area (PPA) analysis is highly desirable. NVIDIA has pioneered programmable GPUs and the CUDA language and is a world leader in high-performance computing technology, with aggressive plans for future processors. This position offers the opportunity to have a real impact in a fast-moving, technology-focused company. What you will be doing: Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro-architecture features to improve the state-of-the-art in GPU memory systems, optimizing along the axes of perf/W, perf/mm, and perf/$. Develop and enhance architecture prototype models for power and noise analysis. Participate in performance and power simulation of features to analyze, define, and improve energy per byte. Analyze benchmarks, application workloads, and performance/power simulation and emulation results to identify areas for architecture optimizations. Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. Collaborate with outside partners on system infrastructure. What we want to see: 10+ yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. Bachelor

What We’re Looking For: We’re looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture. Ideal Background: An ideal candidate will have: Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc Understanding of memory sub-systems and interactions in multi-die systems Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems Strongly Preferred: Experience with multi-die designs Experience with MCM and chiplet based architectures and architectural partitioning across them Experience in partitioning workloads across multiple chips and chip packages

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Architecture Lead in Non-Volatile-Engineering NAND Flash design team at Micron Technology, Inc., your role will cover both pathfinding as well as execution of innovative non-volatile memory designs! You will work with and support the efforts of functional teams to innovate and evaluate key multi-functional features and architecture to ensure best in class memory products in terms of die size, performance, reliability and power. In this role, you are expected to participate in definition of simulation plans, environment setup, pass/fail criteria, and coverage analysis. You will also work closely with design team members during all phases of design from concept to production. In addition, you will actively participate in the design and quality methodology improvements across the department. You will also be responsible for assisting product engineers in post-silicon design validation, root cause analysis, and providing solutions! Responsibilities and Duties include, but not limited to: Innovate and architect innovative memory/storage solution for high performance and energy efficient systems Identify and innovate new concepts and features based on customer requirements Contributing to the development of new NAND Flash Memory by assisting with the overall design, layout, and optimization of Memory/Logic circuits Drive multi-functional team in key features evaluation and recommend decision on architecture Working with Marketing, Probe, Assembly, Test,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Architecture team defines the future of memory systems that enable next-generation AI, machine learning, and high-performance computing applications. By researching advanced memory architectures, system designs, and emerging technologies, the team develops innovative solutions that maximize performance, scalability, and efficiency for future memory products. As a Memory System Architect on the HBM Architecture team, you will contribute to the definition of future memory architectures supporting Generative AI and data-intensive workloads. You will research and evaluate advanced memory system concepts, analyze AI accelerator architectures, and develop models that guide product strategy and technology roadmaps for next-generation memory solutions. Responsibilities Research and evaluate advanced memory architecture concepts for AI accelerators, including GPU, TPU, and emerging compute platforms. Develop and analyze system-level models to assess performance, power, scalability, and efficiency across memory and compute architectures. Investigate memory hierarchy optimizations involving HBM, DRAM, cache, storage, and interconnect technologies. Evaluate architectural trade-offs and emerging technologies, including compute-near-memory concepts, to support future product development. Collaborate with cross-functional teams to translate research findings into architecture recommendations and long-term technology roadmaps.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the team defining the future of packaging of complex memory systems! Our Package pathfinding and Architecture organization sits at the intersection of silicon, packaging, systems, and customer needs—turning complex scaling challenges into technologies that power next generation platforms, through cutting edge packaging technologies. If you enjoy working on problems with real industry impact, look no further! This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end to end memory system architectures, to guide long term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron. Responsibilities: Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance. Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach Drive long‑term memory technology packaging strategy and influence industry standards Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and d

Memory Systems Performance & Workload Architect - SMTS — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: Develop system-level solutions, tools, and methodologies to optimize DRAM performance, power efficiency, and cost. Collaborate with multi-functional teams to ideate, evaluate, and implement innovative DRAM and memory system solutions. Analyze system behavior and assess solution effectiveness, making data-driven optimizations and trade-offs. Drive architectural innovation for current and future generations of DRAM technologies. Communicate complex technical concepts clearly and mentor team members through training and technical guidance. Using AI in applicable job functions Minimum Qualifications: Proven experience in memory design and product engineering, memory specifications and operations, or memory system architecture and usage. Minimum of 7 years of experience in the memory or semiconductor industry. Strong understanding of DRAM architectures and system-level interactions. Ability to analyze complex technical problems and drive solutions. Bachelor’s degree in Electrical Engineering, Physics, Computer Engineering, or a related field, or equivalent experience. Preferred Qualifications: Experience with advanced memory technologies such as LPDDR5/6, DDR5/6, GDDR6/7, or HBM3E/4. Strong analytical and problem-solving skills with a passion for innovation. Ability to identify complex technical challenges and develop creative, scalable solutions. Deep under

Job Title:AI Architect About Us “Capco, a Wipro company, is a global technology and management consulting firm. Awarded with Consultancy of the year in the British Bank Award and has been ranked Top 100 Best Companies for Women in India 2022 by Avtar & Seramount . With our presence across 32 cities across globe, we support 100+ clients across banking, financial and Energy sectors. We are recognized for our deep transformation execution and delivery. WHY JOIN CAPCO? You will work on engaging projects with the largest international and local banks, insurance companies, payment service providers and other key players in the industry. The projects that will transform the financial services industry. MAKE AN IMPACT Innovative thinking, delivery excellence and thought leadership to help our clients transform their business. Together with our clients and industry partners, we deliver disruptive work that is changing energy and financial services. #BEYOURSELFATWORK Capco has a tolerant, open culture that values diversity, inclusivity, and creativity. CAREER ADVANCEMENT With no forced hierarchy at Capco, everyone has the opportunity to grow as we grow, taking their career into their own hands. DIVERSITY & INCLUSION We believe that diversity of people and perspective gives us a competitive advantage. Job Description: Key Responsibilities • Lead solution design from business problem to target architecture, integration and deployment blueprint. • Design single and multi-agent workflows, tool calling, memory, retrieval and human-in-the-loop controls. • Define security, resilience, latency, cost, observability and scalability requirements. • Select models, cloud services, vector search and frameworks; assess build versus buy. • Set standards and guardrails, review designs, and partner with product, cloud and AI governance. • Embed AIDLC in design: stage gates, governance checkpoints and architecture

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary As a DRAM Architect, you will optimize DRAM solutions for power, performance, and cost while pioneering new memory features and system-level innovations. You will collaborate with global, multi-functional teams to deliver high-quality, reliable, and power-efficient DRAM solutions that meet aggressive performance and time-to-market goals. Responsibilities: Develop comprehensive DRAM system/component solutions, specifications, and methodologies to optimize DRAM performance, power efficiency, and cost. Collaborate with multi-functional teams to brainstorm and implement innovative ideas, assess solution efficiency, and make necessary adjustments. Drive innovation in future memory generations within a dynamic work environment. Analyze system behavior and assess solution effectiveness, make data-driven optimizations and trade-offs. Communicate complex technical concepts to engineers from various backgrounds. Minimum Qualifications: 3&#43; years of proven experience in memory design, product engineering, or system architecture and usage Self-motivated with exceptional problem-solving skills and a drive to discover new solutions. Excellent communication and interpersonal skills. Bachelor’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field. <