Architect Memory Subsystem Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define what is possible at the limits of speed and scale. Our architecture team evaluates future interfaces early, using data‑driven analysis to guide product and IO strategy. This role focuses on early‑phase SI architecture exploration. You will independently model, simulate, and assess high‑speed interfaces and translate findings into clear architectural intent and requirements. This role uses AI for work optimization. Responsibilities: Define SI architectural strategies for high‑speed memory and system interfaces Perform early feasibility and scaling analysis for future data rates Build hands‑on channel models across package, board, and system Drive end‑to‑end SI co‑design with IO, package, and system architects Translate SI insights into electrical requirements and architectural constraints Minimum Qualifications: Bachelor’s degree or equivalent practical experience in Electrical Engineering or related field 10&#43; years of experience in signal integrity or high‑speed interface design Strong hands‑on SI modeling and simulation experience Deep understanding of transmission lines, jitter, loss, and crosstalk Preferred Qualifications: Master’s degree in a related technical field Experience with memory interfaces or high‑speed IO standards Background in architecture or pre‑silicon exploration roles Strong communication of complex SI trade‑offs to leadership Experience using AI/LLM productivity tools. <p style="text-

What We’re Looking For: We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs. Ideal Background: An ideal candidate will have: Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options Deep understanding of AI workloads, especially low latency LLM inference Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: Hands-on experience with AI chip architecture and tapeouts End to end ownership of at least one AI ASIC project History of product delivery (regardless of ultimate commercial success of said product) Experience with HBM-based AI chip architecture Experience in proposing “weird” chip architectures (in any domain, not just AI!)

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. DRAM ASIC Architecture Role Overview Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies. This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions. The successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams. Key Responsibilities Define next-generation DRAM &#43; logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation. Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis coverin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7&#43; years or MSEE with 5&#43; years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7&#43; years, or MSEE with 5&#43; years of releva

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a Senior NPU Architect to join our Architecture Team. In this role, you will collaborate with a team of NPU and system architects, hardware engineers, and software teams to define and optimize key features in our AI accelerator with the cutting-edge in-memory computing technology. You will contribute to designing a holistic AI HW/SW solution that has the best performance and efficiency on the market for the latest AI/ML workloads, such as LLMs, diffusion models, CNNs, and more. Responsibilities Define and develop the spec, architecture, and micro-architecture of key architecture modules (such as the in-memory compute unit, on-chip network, and memory orchestration units) based on the requirements of the workloads and software deployment flow Contribute to the modeling of aforementioned key architecture modules in our C++ simulation framework to ensure a functional implementation of the features Collaborate with the design verification team to deliver a strategy and infrastructure for the testing of the architecture features within said modules Work with the software team and other architects to analyze the performance and efficiency of the architecture modules for key workloads, identify performance bottlenecks, and guide architectural decisions Stay up to date with the latest trends and research in AI workloads, architectures, an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and fin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s Compute and Memory Business Unit (CMBU), where we shape how memory powers the world’s most demanding computing platforms. Our team works at the intersection of advanced DRAM technology, system architecture, and emerging AI workloads. We collaborate closely with customers, partners, and internal R&D teams to influence the future of memory-centric system design—and we have a lot of fun doing it! As a Product Architecture Engineer for DRAM, you will play a key role in defining how Micron memory technologies enable AI training and inference platforms. This role blends deep technical exploration with industry engagement and internal collaboration. You will help translate system-level challenges into differentiated DRAM solutions while influencing both customer designs and Micron’s product roadmap. Responsibilities : Explore and evaluate system architectures using modeling, simulation, and prototyping tools Engage customers and partners to identify system bottlenecks and future memory innovations Pathfind AI-focused architectures using LPDDR and DDR DRAM technologies Define and explore DRAM features that increase value in AI and high-performance systems Mentor and coach junior architects and engineers Minimum Qualifications : Bachelor’s degree in Electrical Engineering or equivalent practical experience 10&#43; years of experience in product engineering or product archit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has advanced the world’s most innovative memory and semiconductor technologies. As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next‑generation high‑bandwidth memory products. You will evaluate block‑level and full‑chip functionality, solve complex challenges in building, and collaborate with a distributed team to deliver highly reliable, industry‑leading HBM solutions. This role provides the opportunity to contribute to groundbreaking DRAM design, TSV‑based 3D integration, and high‑speed mixed‑signal architectures supporting Machine Learning and AI applications. Responsibilities Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Member of Technical Staff HBM Design Architect, you will be responsible for design and development of high-speed interface between DRAM and Base die in HBM cube! This includes designing the DRAM command and control logic, as well serializing and de-serializing scheme. You will collaborate with a highly creative and motivated development team applying brand-new memory technologies to build groundbreaking HBM products! Responsibilities: Responsible for the high-speed DRAM and Base die interface in HBM cube. Design the DRAM command and control logic, as well as serializing and de-serializing scheme at the interface. Conduct circuit simulations using standard industry simulators such as FINESIM, HSPICE and VERILOG Collaborate with data path design on floor planning and full chip testbench. Analyze timing/area/power in high-speed DRAM or mixed-signal design. Contribute to the development of new HBM product opportunities by assisting with the overall design, layout, and optimization of Memory, Logic, and Analog circuits. Qualifications: Extensive experience with DRAM operation and JEDEC specifications across DDR, LPDDR, GDDR, and HBM product families. Strong technical expertise in analog and mixed-signal circuit design. Hands-on proficiency in DRAM command decoding, bank logic, and RAS/CAS chain design. Demonstrated innovation and problem‑solving capabilities in

At FourKites we have the opportunity to tackle complex challenges with real-world impacts. Whether it's medical supplies from Cardinal Health or groceries for Walmart, the FourKites platform helps customers operate global supply chains that are efficient, agile and sustainable. Join a team of curious problem solvers that celebrates differences, leads with empathy and values inclusivity. As a Principal AI Architect, you will own the architecture underneath every FourKites AI agent: the harness they run in, the context they see, the models they call, and the evals that tell us whether they work. Our digital workers (Tracy for track and trace, Sam for supplier operations, Alan for appointment management, Cassie for customer service, Polly for document management, and more on the way) do real supply chain work on a shared platform, and you will set its direction. This is a hands-on individual contributor role based in Chennai (hybrid). You'll write code most weeks, lead design reviews across agent teams, and make the calls on model choice, context strategy and evaluation that every team builds on. What you’ll be doing: Define the reference architecture for FourKites agents: the agent loop, tool execution, state and checkpointing, retries and recovery, guardrails, permissions, and human-in-the-loop handoffs Design for long-running, multi-step work that spans many context windows and recovers cleanly when a tool, carrier API or model call fails Decide where each problem is best solved (frontier LLM, open-weight model, fine-tuned encoder, or plain code) and own model routing, cost-per-task and latency budgets across the fleet Integrate agents with FourKites' event-driven platform (Kafka, microservices, Postgres) and with customer systems through APIs and MCP servers Set the standard for what goes into an agent's context window (system prompts, tool definitions, retrieved documents, memory, prior turns) within an explicit token budget Build shared components for retrieval,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary – Member of Technical Staff - Agentic AI Architect, Smart Manufacturing AI Pathfinding & Innovation (AIPI) Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The memory solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. The Smart Manufacturing and AI team at Micron Technology is looking for an ambitious engineer (Member of Technical Staff | MTS) to deliver industry-winning Agentic AI solutions that power Micron’s dominance in the highly competitive memory solutions market. This role sits at the intersection of applied Agentic AI engineering and production systems work: you will architect autonomous AI Agents and the agentic and data pipelines that power them, build robust CI/CD deployment paths to Kubernetes and containers, and push the limits of agent performance profiling and evaluation to turn massive data and compute into measurable manufacturing impact. Qualified applicants will have experience across data/cloud technologies and systems engineering, with extensive practice modeling data, querying, and deploying scalable pipelines to execute AI agents. You will collaborate with Data Scientists, Data Engineers and expert users to build and deploy scalable Agentic AI solutions th

NVIDIA is seeking a Senior System Architect: Heterogeneous EDA Systems to solve a complex challenge in accelerated computing: Failure Attribution at Scale. As EDA or equivalent experience workloads scale across thousands of heterogeneous nodes, a single failure can cause massive resource waste. We need an engineer to develop and build an automated framework. This framework will ingest telemetry from CPU and GPU clusters to identify the root cause of job failures in real-time. It will distinguish between hardware faults, infrastructure instability, and software defects. What you'll be doing: Architect Failure Attribution Frameworks: Build a scalable &#34;flight recorder&#34; for EDA jobs that captures high-fidelity state across the CPU, GPU, and Fabric at the moment of failure. Build automated diagnostics that correlate GPU XID errors, PCIe bus failures, and CUDA memory exceptions. Connect these errors with system-level events such as OOM kills or NUMA-related hangs. Distributed Logging & Tracing: Implement low-overhead tracing mechanisms (using tracing tools or custom agents) that provide access to job execution across multi-node Slurm or Kubernetes clusters. Root Cause Automation: Develop heuristics and models based on machine learning to classify failures as &#34;Hardware Fault,&#34; &#34;Software Bug,&#34; or &#34;Environment Issue.&#34; This reduces the Mean Time to Identify (MTTI) for R&D teams. Resiliency Engineering: Work closely with hardware and infrastructure teams to define &#34;signals of impending failure,&#34; enabling proactive job migration or check-pointing before a crash occurs. What we need to see: Distributed Systems Mastery: BS, MS, or PhD in Computer Science or Electrical Engineering (or equivalent experience) with 6&#43; years in systems programming. Experience building automated

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a CPU Cluster Performance Architect to help shape the performance and scalability of our next-generation CPUs. You’ll focus on how multiple CPU cores work together as a cluster — from cache hierarchies and coherent interconnects, to memory bandwidth and overall system behavior. This is a hands-on architecture role for someone who enjoys using performance models and simulation to understand bottlenecks, explore tradeoffs, and influence decisions early in the design process. You’ll work closely with CPU architects, RTL designers, software and compiler teams, and system architects to understand workload behavior and turn performance insights into architectural improvements. If you enjoy looking at the entire cluster and how performance scales across cores, memory systems, and chiplets, this is an opportunity to have a significant impact. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a strong foundation in CPU microarchitecture and performance, with an understanding of how cores, caches, interconnects, and memory systems interact. You enjoy using modeling,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview Our Munich engineering team develops mixed‑signal and IO solutions for next‑generation memory technologies. The group partners closely with global analog, digital, and product teams throughout the design and silicon lifecycle. Role Overview We are hiring an IO Design Architect to design new architecture, analysis, and validation of high‑speed memory IO. This role combines hands‑on circuit understanding with system‑level thinking and close collaboration across multiple design teams. Responsibilities Define and own the IO and PHY concepts for high‑speed memory interfaces Perform block‑level simulation, analysis, and feasibility checks Review and guide schematic‑level implementation to align with architectural intent Support verification, silicon bring ‑up, and debug activities Collaborate with