Architect Subsystem Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions that enable advanced AI, high-performance computing, data center, and networking applications. Our team collaborates across architecture, RTL design, verification, physical design, firmware, and product engineering to deliver innovative memory-centric SoC solutions that meet demanding power, performance, area, quality, and schedule objectives. As an HBM SoC Design Engineer/Architect, you will contribute to the design, integration, and validation of advanced HBM logic die and memory-centric SoCs. Working alongside experienced engineers, you will apply knowledge gained through academic coursework, research, internships, and engineering projects to solve real-world semiconductor design challenges. This role offers opportunities to develop expertise in digital design, ASIC development, HBM architecture, and AI-enabled engineering methodologies that improve design productivity and quality. Responsibilities Design, implement, and integrate digital logic and subsystem RTL using Verilog or SystemVerilog for next-generation HBM SoC solutions. Collaborate with architects and multi-functional engineering teams to translate functional requirements into microarchitectures, interface definitions, and implementation plans. Support design-quality activities including simulation, synthesis, static timing analy

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a Senior SSD Firmware Architect, you will be the visionary behind the intelligence of our proprietary DirectFlash™ technology, fundamentally decoupling storage software from commodity hardware limitations. You will architect high-performance firmware that harmonizes custom controller SoCs with NAND media to deliver unprecedented density and reliability for enterprise and hyperscale environments. By leading the technical strategy between hardware, silicon vendors, and systems teams, you ensure our storage modules don't just store data—they redefine how the world accesses it. WHAT YOU'LL DO Define and drive the firmware architecture for next-generation DirectFlash™ SSD modules, including subsystem design, firmware modularization, and system integration. Work with controller vendors and hardware teams to bring up new SSD controller SoCs and enable features such as PCIe, NAND interfaces, power-loss protection, and telemetry. Develop firmware components supporting NVMe and OCP SSD specifications, ensuring compliance, performance, and interoperability. Debug complex cross-layer issues involving firmware, controller hardware, NAND media, and host systems. Improve SSD data path performance and latency through firmware design and analysis. Review designs, mentor engineers, and improve development tools, testing, and automation. We are primarily an in-office environment and therefore, you will be expected to work from th

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal HBM RTL Designer, you will serve as a technical leader driving the front‑end digital design of next‑generation High Bandwidth Memory (HBM) products. This role requires deep expertise in RTL architecture, build methodology, and multi-functional technical leadership. You will own complex design blocks end‑to‑end—from architectural definition through production‑quality implementation—while mentoring engineers, influencing design strategy, and ensuring world‑class design execution. Responsibilities: Define, architect, and lead the development of advanced RTL blocks for HBM subsystems, ensuring alignment with product requirements and architectural goals. Own end‑to‑end front‑end design, including micro‑architecture, RTL development, simulation strategy, and design quality. Drive technical decisions across circuit development, synthesis, constraints, and physical‑design integration, ensuring timing, power, and area compliance. Champion design methodologies, develop reusable frameworks, and improve RTL design flows, validation strategies, and sign‑off processes. Collaborate closely with physical design, verification, architecture, and product engineering to integrate subsystems and deliver high‑quality silicon. Lead root‑cause analysis and corrective actions for complex design issues, ensuring long‑term design robustness. Communicate effectively at all levels, contributing to technical planning, project execution, and cross‑organizational alignment. Minimum Qu

About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands-on engineering, and creative approaches to building complex hardware. About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre-silicon validation, silicon bring-up, and post-silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end. In this role, you will: Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes,

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join our team as a Senior SSD Firmware Lead / Architect and help define the future of data storage. In this role, you will lead the architecture and development of firmware for our industry-leading DirectFlash™ SSD Modules, which power Pure Storage platforms used by both enterprise and hyperscale customers. You will work closely with hardware engineers, controller vendors, and systems teams to design firmware architecture, bring up new hardware platforms, and improve performance and reliability. WHAT YOU'LL DO Define and drive the firmware architecture for next-generation DirectFlash™ SSD modules, including subsystem design, firmware modularization, and system integration. Work with controller vendors and hardware teams to bring up new SSD controller SoCs and enable features such as PCIe, NAND interfaces, power-loss protection, and telemetry. Develop firmware components supporting NVMe and OCP SSD specifications, ensuring compliance, performance, and interoperability. Debug complex cross-layer issues involving firmware, controller hardware, NAND media, and host systems. Improve SSD data path performance and latency through firmware design and analysis. Review designs, mentor engineers, and improve development tools, testing, and automation. WHAT YOU BRING Extensive experience developing SSD firmware for enterprise or hyperscale systems, with strong knowledge of SSD architecture and controller design. Solid underst

About the Team Our Robotics team is focused on unlocking general-purpose robotics and pushing towards AGI-level intelligence in dynamic, real-world settings. Working across the entire model stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the constraints of physical systems to improve peoples’ lives. About the Role We’re looking for a Robotics Control Systems Engineer to take on a foundational role within our robotics team. You’ll help architect, implement, tune, and verify the control infrastructure that enables intelligent, reliable, and responsive robot behavior. This is a deeply hands-on role focused on real-time systems, actuation, dynamics, low-level hardware interaction, and whole-robot performance. You’ll spend significant time working directly with robots onsite: debugging behavior, tuning subsystems, running experiments, and providing feedback across mechanical, electrical, and software teams. This role is based in San Francisco, CA, and requires in-person 5 days a week. In this role, you will: Design and implement real-time control algorithms for robotic systems, including motion control, feedback loops, state estimation, actuator control, and subsystem tuning. Define the control architecture from low-level actuators and hardware interfaces through whole-robot behavior and policy. Identify and characterize actuator, hardware, and software parameters through rigorous experimentation, testing, commissioning, and verification. Work with machine learning engineers to implement reinforcement learning models. Collaborate across mechanical, electrical, and software teams to integrate control logic with sensing and actuation hardware. Help inform the mechanical and electrical design to maximize capability and flexibility. Create the control system architecture; determine the correct level of abstraction from actuators all the way up to whole-robot

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems. Experienced in CPU

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities: Design and implement robust, scalable, and secure RESTful APIs; Develop applications on embedded platforms, integrating closely with hardware and network systems; Architect and document backend software systems with a focus on performance, maintainability, and scalability; Perform network programming and system-level integration across multiple subsystems; Collaborate with cross-functional teams including Frontend Engineering, UX Design, and QA to ensure cohesive product development; Ensure high-quality deliverables and meet project timelines consistently; Participate in code reviews and actively share knowledge to foster a culture of continuous improvement. Requirements: 5+ years of experience with Golang in a production environment; 5+ years of experience working with relational databases (RDBMS) such as PostgreSQL or MySQL; Demonstrated expertise in designing and developing RESTful APIs; Strong analytical and problem-solving skills, with a proactive and adaptable mindset; Proficiency in AI development environments (e.g., Cursor, Claude Code) and expertise in AI development techniques, such as Spec-Driven Development, are required; Fluent in English. Nice to have: Experience developing or maintaining IoT platforms or connected device ecosystems; Knowledge of IoT protocols such as MQTT, CoAP, or WebSockets for

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities: Design and implement robust, scalable, and secure RESTful APIs; Develop applications on embedded platforms, integrating closely with hardware and network systems; Architect and document backend software systems with a focus on performance, maintainability, and scalability; Perform network programming and system-level integration across multiple subsystems; Collaborate with cross-functional teams including Frontend Engineering, UX Design, and QA to ensure cohesive product development; Ensure high-quality deliverables and meet project timelines consistently; Participate in code reviews and actively share knowledge to foster a culture of continuous improvement. Requirements: 5+ years of experience with Golang in a production environment; 5+ years of experience working with relational databases (RDBMS) such as PostgreSQL or MySQL; Demonstrated expertise in designing and developing RESTful APIs; Strong analytical and problem-solving skills, with a proactive and adaptable mindset; Proficiency in AI development environments (e.g., Cursor, Claude Code) and expertise in AI development techniques, such as Spec-Driven Development, are required; Fluent in English and Latvian. Nice to have: Experience developing or maintaining IoT platforms or connected device ecosystems; Knowledge of IoT protocols such as MQTT, CoAP, or Web

For more than 30 years, SonicWall has delivered a partner-first unified cybersecurity portfolio that helps SMBs, MSPs, and IT teams consolidate network security, endpoint security, security service edge (SSE), and threat response across hybrid environments. By bringing connected technology, real-time threat intelligence, automation, and expert services together, SonicWall helps organizations simplify security operations, achieve better security outcomes, and lower total cost of ownership. Backed by a global ecosystem of more than 17,000 partners, SonicWall delivers enterprise-grade protection built for SMB and mid-market realities. For more information, visit www.sonicwall.com or follow us on X, LinkedIn , Facebook , and Instagram . About the Role SonicWall is seeking a Senior Software Engineer with deep IPv6 expertise to lead the design, implementation, and hardening of IPv6 capabilities across the Sonicwall firewall firmware stack. As a Principal Engineer, you will be the technical authority for IPv6 feature parity, protocol correctness, and interoperability across SonicWall Next-Generation Firewall (NGFW) platforms. This role is ideal for engineers with hands-on experience delivering IPv6 in high-performance router, switch, or carrier-grade networking products who are looking to apply that expertise in the embedded network security domain. Responsibilities Lead IPv6 Architecture & Feature Delivery — Own end-to-end design and implementation of IPv6 features across the Sonicwall frewall networking stack, including IPv6 routing, interface addressing, DHCPv6, NDP, MLDv2, and IPv6 Policy-Based Routing (PBR). Drive IPv6 Feature Parity — Identify and close gaps between IPv4 and IPv6 feature sets across subsystems — including VPN Tunnel Interfaces, IPsec/IKEv2, SSL-VPN, Syslog, SNMP, and NAT64 — ensuring consistent dual-stack and IPv6-only operation. Design High-Performance IPv6 Packet Processing Paths — Architect and optimize the IPv6 datapl

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Join forces with us on our mission to build a better IT industry. We are currently looking for a highly skilled Backend Software Engineer (Go) to our team in Stockholm or Malmö, Sweden. Please note that applicants must live in Sweden and hold a valid work permit at the time of application to be considered for this role. Responsibilities: Design, develop, and maintain efficient, scalable, secure, and reliable backend services for UniFi OS and/or other applications across UniFi Design and implement robust RESTful APIs and services using Golang Develop applications and services for embedded platforms, integrating closely with network device firmware, hardware, and other applications Architect and document backend software systems with a focus on performance, scalability, security, and maintainability Perform network programming and system-level integration across multiple subsystems Integrate new features into larger software systems and connected device ecosystems Collaborate closely with cloud architects, backend and frontend engineers, UX designers, QA engineers, and other stakeholders to deliver cohesive product experiences Participate in code reviews, technical discussions, and knowledge sharing to continuously improve engineering quality and practices Take ownership of deliverables and consistently meet project timelines and q

SonicWall is a cybersecurity forerunner with more than 30 years of expertise and is recognized as a leading partner-first company, ensuring our partners and their customers are never alone in the fight against cybercrime. With the ability to build, scale and manage security across the cloud, hybrid and traditional environments in real-time, SonicWall provides relentless security against the most evasive cyberattacks across endless exposure points for increasingly remote, mobile and cloud-enabled users. With its own threat research center, SonicWall can quickly and economically provide purpose-built security solutions to enable any organization—enterprise, government agencies and SMBs—around the world. For more information, visit www.sonicwall.com or follow us on Twitter , LinkedIn , Facebook and Instagram . About the Role SonicWall is seeking a Software Dev Senior Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+. Responsibilities Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover. Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate. Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency. High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About the Team At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team develops future High-Bandwidth Memory (HBM) architectures, PHY design methodologies, and automation solutions that enable next-generation AI, high-performance computing, networking, and data center applications. The team works closely with Architecture, Design Engineering, Verification, Product Engineering, and external partners to advance memory technologies while improving design quality, productivity, and development efficiency. Position Overview As a Senior or Graduate Engineering Intern, you will collaborate with experienced HBM architects and engineers to support the development of digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next-generation HBM PHY and IO subsystems. This role offers hands-on experience in digital design, verification, automation, and timing analysis, while providing opportunities to leverage AI Assisted engineering workflows, Large Language Models (LLMs), and Generative AI tools to enhance engineering productivity and design efficiency. Responsibilities Support digital design, integration, and timing analysis activities for HBM PHY and IO subsystems, including timing constraint development and timing closure efforts. Develop an

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP. You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies. You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify. Work with HW architects and designers to make the right implementation choices. You will be working with architects, designers, and other members of yo