Architect Subsystem Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. HBM Design Architecture — Principal Engineer Role Overview We are seeking a highly motivated HBM Design Architecture Engineer (Principal Engineer) to drive exploration and definition of next‑generation AI memory and system environments. In this role, you will analyze emerging infrastructure trends, build performance models, and develop/extend tooling that informs HBM architecture decisions and system‑level trade‑offs. You will work closely with architects and senior engineers across DTPCO, Design, and Product/System teams to translate AI workload requirements into actionable memory subsystem and architectural intercept strategies. Key Responsibilities You will own and contribute to projects such as: Research and synthesize emerging trends in compute, networking, and storage infrastructure to anticipate how future AI systems will evolve. Lead HBM architecture analysis by defining bandwidth/latency targets, identifying constraints, and translating workload and system data into actionable memory requirements. Develop and maintain simulation frameworks to model AI cluster performance and memory subsystem behavior; validate models against internal and external benchmarks. Build and apply first‑order performance models spanning HBM bandwidth/latency, GPU/CPU interactions, and memory hierarchy trade‑offs to guide architectural decisions. Create and curate trend dashboards using CSP benchmar

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Memory Systems Engineering team and contribute to the development of premier digital and mixed-signal foundations for our high-bandwidth memory (HBM) products. This position offers an outstanding chance to work intimately with multiple engineering areas, guaranteeing the smooth integration and implementation of HBM base die. Join a motivated team committed to delivering robust first-pass silicon that meets our strict bandwidth, latency, power, and reliability objectives! Responsibilities Assist in defining and carrying out digital micro-architecture for HBM base-die subsystems, covering channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance counters, and reliability features. Translate system requirements into timing, power, and area considerations by partnering with physical layer and system architects, and help maintain interface specifications for bus protocols, clock-domain crossings, and reset strategies. Implement and integrate synthesizable SystemVerilog RTL, including multi-channel logic, interrupts, events, register maps, scan hooks, and design-for-test interfaces, while supporting clean integration and ECO flows. Collaborate with design verification teams to support verification planning, coverage goals, CDC/RDC checks, and debugging of RTL, testbench, and gate-level issues. Support silicon bring-up and post-silicon validation through debug enablement, issue correlation to RTL or architecture, and col

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

What if the work you did every day could impact the lives of people you know? Or all of humanity? At Illumina, we are expanding access to genomic technology to realize health equity for billions of people around the world. Our efforts enable life-changing discoveries that are transforming human health through the early detection and diagnosis of diseases and new treatment options for patients. Working at Illumina means being part of something bigger than yourself. Every person, in every role, has the opportunity to make a difference. Surrounded by extraordinary people, inspiring leaders, and world changing projects, you will do more and become more than you ever thought possible. Responsibilities Responsible for single or multiple major project initiatives, from inception to production; develops new technologies, methods, and processes to meet the objectives of the company. Owns/designs/architects one or more large subsystems. Contributes to interdepartmental and external schedules and for delivery of projects within the overall time frame and budget established jointly with management. Contributes to/influences strategic plans. Leads by example the automation and implementation of highly available and resilient platforms in public clouds, without manual or direct intervention Anticipates problems well in advance, proposes solutions, and drives to conclusion. An escalation point and expert in leading investigation/resolution of complex technical problems across the Informatics global estates. Researches, drives innovation and leads efforts to apply relevant industry concepts and technologies in the department. Evaluates industry solutions, Drives internal collaborations and able to present key technical recommendations while considerin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets. In this role, y ou'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows. Responsibilities Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features. Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures. Develop, integra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role passionate about RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer

About the Team OpenAI’s Hardware organization develops system and infrastructure solutions designed for the unique demands of advanced AI workloads. We work closely with architecture, infrastructure, and vendor teams to evaluate system performance and guide critical design decisions. Our team focuses on building and applying performance modeling frameworks to understand system behavior, quantify tradeoffs, and inform next-generation infrastructure design. About the Role We are seeking Performance Modeling Engineers to develop and apply modeling tools that evaluate AI system performance and inform architectural decisions. In this role, you will work closely with the Performance Modeling Lead and partner teams to analyze system behavior, run simulations or analytical models, and help quantify tradeoffs across compute, memory, networking, and storage. You will contribute to building modeling frameworks and applying them to real-world questions that impact system design and vendor decisions. This role is well-suited for engineers with strong software or modeling backgrounds who are interested in developing deeper expertise in system architecture and AI infrastructure. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Develop and maintain performance modeling tools and frameworks. Build models to evaluate system behavior across: compute, memory, and interconnect subsystems distributed system scaling and bottlenecks. Run simulations and analytical models to support architectural tradeoff analysis. Collaborate with performance modeling lead and system architects to answer forward-looking design questions. Analyze and interpret modeling outputs, translating results into actionable insights. Validate models against real system measurements and workload behavior. Contribute to improving modeling fidelity, usability, and scalability. Qualifications Strong software engineeri

Job Details: Job Description: The Role and Impact As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development. Business Group You will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry. Key Responsibilities - Define and develop scalable and reusable block, subsystem, and SoC verification plans. - Create test benches and verification environments that align with microarchitecture specifications. - Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs. - Debug and root cause issues in presilicon environments, implementing corrective measures to address failures. - Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features. - Document and maintain test plans, driving technical reviews with design and architecture teams. - Integrate security coverage activities within test plans, including regression and debug tests. - Maintain and improve

Zoox’s Robot Software Infrastructure Deployment team builds the critical systems that flash and update software and firmware across our vehicles and test fixtures—spanning development, manufacturing, and fleet operations. Our deployment system orchestrates updates across a massive ecosystem: advanced sensors, high-performance compute platforms, automotive ECUs, network switches, and user interface devices. Because of the sheer breadth of this domain, this role offers a unique vantage point. You will maintain a high-level view of our entire architecture while possessing the sharp technical acumen to dive deep into specific components when solving complex engineering challenges. If you thrive on variety, collaboration, and high-impact infrastructure, this team is for you. In this role, you will: Expand Capability: Design and integrate deployment support for next-generation vehicle components and subsystems. Architect Infrastructure: Enhance the core deployment framework, developer tools, instrumentation, and integrations with broader engineering systems. Optimize Performance: Drive systemic improvements in deployment speed, efficiency, and mission-critical reliability. Root-Cause Failures: Triage, debug, and resolve complex deployment failures across hardware and software boundaries. Collaborate Cross-Functionally: Partner closely with Firmware, QA, Systems, Manufacturing, and Fleet Operations teams to ensure seamless end-to-end execution. Qualificat

Architect - Enterprise Application - ServiceNow N Ready to turn bold ideas into real-world impact? At Genpact, we don’t just adapt to change, we lead it. AI and digital innovation are transforming the way businesses work, and we’re at the forefront of it. Genpact’s AI Gigafactory , our industry-first accelerator, exemplifies how we scale advanced technology solutions to help global enterprises work smarter, grow faster, and transform at scale. Whether tackling complex challenges through large-scale models or agentic AI , our breakthrough solutions tackle companies’ most complex challenges. If you thrive in a fast-moving, innovation-driven environment, love building and deploying cutting-edge AI solutions, and want to push the boundaries of what’s possible, this is your moment. Genpact (NYSE: G) is an agentic and advanced technology solutions company. We leverage process intelligence and artificial intelligence to deliver measurable outcomes. With a strong partner ecosystem and decades of client trust, we provide innovative solutions that transform how businesses run. Powered by a team with an active learning mindset and client centricity at its core, we deliver lasting value for the world’s leading enterprises. Get to know us at genpact.com and on LinkedIn , YouTube , X , and Facebook . Job Description • Design and architect ServiceNow solutions that align with business require

Architect - Enterprise Application - SAP N Ready to turn bold ideas into real-world impact? At Genpact, we don’t just adapt to change, we lead it. AI and digital innovation are transforming the way businesses work, and we’re at the forefront of it. Genpact’s AI Gigafactory , our industry-first accelerator, exemplifies how we scale advanced technology solutions to help global enterprises work smarter, grow faster, and transform at scale. Whether tackling complex challenges through large-scale models or agentic AI , our breakthrough solutions tackle companies’ most complex challenges. If you thrive in a fast-moving, innovation-driven environment, love building and deploying cutting-edge AI solutions, and want to push the boundaries of what’s possible, this is your moment. Genpact (NYSE: G) is an agentic and advanced technology solutions company. We leverage process intelligence and artificial intelligence to deliver measurable outcomes. With a strong partner ecosystem and decades of client trust, we provide innovative solutions that transform how businesses run. Powered by a team with an active learning mindset and client centricity at its core, we deliver lasting value for the world’s leading enterprises. Get to know us at genpact.com and on LinkedIn , YouTube , X , and Facebook . Job Description • Designing and creating SAP architecture blueprints; Leading SAP implementation projec

About the Team The Tax Technology Automations & Innovation team — known internally as the AI Team — builds the automations, Generative AI, and internal tooling that let DoorDash's global Tax function scale as the business grows across the US, Canada, and — through Wolt and Deliveroo — internationally. We turn manual, repetitive tax work into reliable, governed software, and we bring modern AI into the heart of how a tax function operates — responsibly, and with auditability built in. The team is organised into an AI Strategy function and three regional pillars: EMEA, US & Canada, and Coffee & Special Projects. This role sits in the AI Strategy function and reports to the Tax Technology lead. You will set the technical and AI direction the three regional pillars build around, and partner across Tax, Tax Tech, Data Operations, Accounting, Product, and Engineering, as well as InfoSec, Internal Audit, and Compliance. About the Role DoorDash is looking for a senior-level AI and data expert to lead how the Tax department operates through automation, Generative AI, and intelligent data tooling. Beyond building high-impact automation, you will set the strategy for how LLMs, GenAI, and machine learning are integrated into critical tax workflows at scale, and act as the AI authority for the function. This is the role that makes the entire team AI-native rather than merely AI-assisted. By owning the AI and automation governance framework, you will also ensure that everything the team builds on top of sensitive tax data stays controlled, defensible, and audit-ready. You don't just build — you set the bar, mentor the regional teams, and decide how we adopt a fast-moving technology responsibly. You're excited about this opportunity because you will… Define and lead the GenAI strategy for the Tax function, identifying high-value use cases and setting adoption standards. Architect and deploy enterprise-grade AI solutions — intelligent assistants, AI-driven classificatio

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: As Architect for the Data Centers & Workplace, you will lead the strategic planning, design, and execution of facilities and infrastructure solutions for SpaceXSI's data centers and site builds. Drawing on expertise in complex, multi-stakeholder projects, you'll collaborate across engineering, procurement, construction, and business teams to deliver integrated, compliant designs that align with aggressive timelines and innovation goals. This position reports to the Facilities Leadership team and is an opportunity that requires travel to different locations and cross-site collaboration. RESPONSIBILITIES: Plan, design, and support the construction of advanced data centers and AI infrastructure, including high-performance computing facilities at new and existing sites. Collaborate with civil, structural, MEP, and fire protection disciplines, as well as procurement and construction teams, to develop integrated solutions optimized for scalability, efficiency, and reliability. Create Basis of Design documents and Request for Quotation (RFQ) packages for external consultants, architects, and vendors; respond to RFIs and iterate based on feedback. Conduct site visits