Design Manager Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (T

What We’re Looking For: We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal Background: An ideal candidate will have: Hands-on experience with multiple advanced node tapeouts Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts Understanding of PPA improvement and what levers exist for each level of the stack Ability to think creatively about methodology for fast design iterations Nice to Have: Hands-on experience with ASIC design process for large die (ideally reticle max) chips Hands-on experience with ASIC design process for AI chips Hands-on experience with multi-die/multi-chiplet/MCM designs

Location: Remote - SF / Boston / Austin Employment: Full-time Level: — Design our custom lasers and their integration with the wafer-scale interposer. You will contribute to our first- and second-generation custom laser designs, and to their integration with the wafer-scale interposer. Responsibilities Owning aspects of qualification and ramp up of VCSEL array product line from design and epitaxy through fabrication, testing and packaging at contract manufacturers. Working with epitaxial wafer vendors and contract manufacturers to ensure epitaxy and mask/fabrication designs can be successfully implemented and repeatably produced. Working with the electronics, packaging and wafer-scale interposer teams to improve the VCSEL design for the integrated interposer product, balancing density, yield and manufacturability tradeoffs in a novel architecture. Working with laser team to set technical direction/road map based on integrated interposer needs. Driving design reviews of VCSEL with other teams Requirements Deep understanding of VCSEL epitaxy design, fabrication design and process, validation, and qualification Experience taping out VCSEL epitaxy and mask/fabrication processes Hands-on experience contributing to an industry-first laser design Ability to work independently as well as in cross-functional teams including electronics, packaging Nice to have Experience using outsourced contract manufacturers for large volume production of VCSELs Experience with high-density VCSEL arrays and VCSEL polarization stabilization High speed direct modulation laser diode design/test experience Understanding of sources of process variation and statistical process control for yield improvement Laser packaging and/or reliability experience

What We’re Looking For: We’re looking for PIC (photonic integrated circuit) design engineers to contribute to and own aspects of the wafer-scale photonic interposer PIC. This will involve solving unique problems in creative ways, such as the tension between density and manufacturability yields, dealing with process variation on large scale wafers, etc. Ideal Candidates: Ideal candidates will have: Experience with both passive and active PIC design components An understanding of the fundamental physics at play, not just a “simulate and turn the crank” attitude Experience with large device count PIC tapeouts Deep understanding of optical coupling in and out of the PIC, especially how to achieve very low losses under realistic manufacturing conditions (alignment, etc) Understanding of the physical manufacturing process behind PICs Nice to Have: Experience with high speed optical communications PICs Experience in designing with PIC material platforms other than silicon photonics (eg InP, TFLN, SiN, polymers, glass, etc) Experience and knowledge of active gain chip integration (eg integrated lasers, SOAs, etc) Experience with large area PICs Understanding of sources of process variation, statistical process control, etc

Datadog is entering a new chapter in how our product looks, feels, and operates. Our Design Lab is defining a new visual direction for the platform, and we’re looking for a Senior Staff Visual Product Designer to help turn that direction into a coherent product experience. Datadog is dense, technical, and used by people working through complex problems—often under real pressure. The challenge is not simply applying a new aesthetic. It is rethinking hierarchy, layout, navigation, interaction, and product patterns so the experience becomes clearer, more cohesive, and more expressive without losing the power our users rely on. This is a hands-on product design leadership role for someone who combines strong visual judgment with deep product and systems thinking. You’ll work alongside visual designers, motion designers, product designers, Design Systems, and Engineering to ensure the new direction changes how Datadog works—not just how it looks. What You'll Do Co-develop Datadog’s next visual direction by applying and stress-testing it across representative product journeys. Translate visual principles into concrete decisions about hierarchy, layout, navigation, information architecture, interaction, and behavior. Use visual language to clarify complex, data-dense experiences — hierarchy, density, and attention. Hold the visual quality bar across work you don't own, and align teams around it. Prototype, test, and refine new patterns before they become systemized. Partner deeply with Product Design, Design Systems, and engineering to turn successful concepts into durable system guidance and implementation. Create clear artifacts, pilots, and narratives that help teams adopt the direction and raise the product quality bar. Influence stakeholders across design, engineering, product, and executive partners. You will report directly to the Design Director and work as part of a small, focused team defining the future state before it scales across hundreds

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview At the Munich Development Center, we develop high-performance memory solutions for the graphics and AI markets. As part of the DRAM Design Engineering Group (DDEG), we collaborate closely with Micron’s global development and manufacturing teams. Our mission is to push the boundaries of memory technology through innovation, precision, and partnership. Role Overview We are looking for a motivated and curious working student or Master’s thesis candidate to join our DRAM design team. This is an outstanding opportunity to gain hands-on experience in integrated circuit (IC) design while working alongside expert engineers in a collaborative, startup-like environment. You will contribute to real-world projects and receive mentorship to support your academic and professional growth. Responsibilities Support the design and simulation of analog or digital circuit blocks under guidance Assist in developing schematics at the transistor level or RTL Participate in functional verification and layout reviews Contribute to testbench development and simulation setup Document design processes and results for internal use or academic reporting Collaborate with cross-functional teams to understand the full memory design flow Leverage generative AI tools to complete tasks in effective manner Optionally: define and complete a master’s thesis project aligned with team goals Required Qualifications Enrolled in a Bachelor’s or Master’s program in Ele

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ***This position is located in our Tel -Aviv Office (ToHa Building, near HaShalom train station) *** Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology seeks an RTL design engineer to develop digital blocks from specification through RTL implementation with strong emphasis on power-efficient, implementation-aware building. In this role, you will work hands-on with synthesis and timing/power analysis tools to develop power, performance, and area (PPA) trade-offs. You will collaborate with multi-functional teams to improve the quality of advanced flash memory products. Responsibilities Develop and implement RTL for digital and mixed-signal blocks using System Verilog. Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR. Design power- and area-efficient RTL with a focus on reducing switching activity, clock power, and leakage. Complete RTL- and gate-level power and timing evaluation to identify and resolve PPA bottlenecks. Collaborate with verification, synthesis, and physical design teams to achieve timing closure and design targets. Minimum Qualifications Bachelor’s degree wi

What We’re Looking For: We’re looking for PCB design engineers to design and own various PCB boards that are components in the A-0 and A-1 system assemblies. Ideal Background: Experience with high power density PCB design, validation and bringup Experience with chip package and PCB board interactions and design for manufacturing Experience with designing and validating high layer count and large format board designs Nice to Have: Experience with very high density (eg HDI PCBs) boards Experience with PCBs with unique materials and unique thermal or mechanical properties Experience with emerging PCB board technology, eg mSAP or other additive methods

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

What We’re Looking For: We’re looking for mechanical design engineers to contribute to, and own aspects of the wafer-scale assembly, including the interactions between the power delivery system, mechanical chassis, heatsink and more. Ideal Background: Track record of solving one or more challenging mechanical engineering problems where the solution was something different than “the usual solution to this type of problem, slightly tweaked” Experience with high power density compute trays, chassis and/or racks. Experience working with multi-material assemblies with mismatched CTEs Nice to Have: Experience with solder joint reliability Experience with large physical size IC packages and assemblies Experience with CoWoS package assemblies Experience with optical system assemblies Experience with mechanical aspects of liquid cooled assemblies

itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration. Location: Hybrid in Carlsbad, CA or Allentown, PA , or U.S. Remote . Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST). Duration: 14 months We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities: Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging. Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs. Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures. Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability. Collaborate with physical design, validation, and hardware engineering teams throughout the complete silicon product lifecycle. Design, validate, and release ATPG patterns while supporting manufacturing test readiness and production ramp. Develop technical solutions and resolve complex DFT challenges with minimal supervision while providing technical leadership to the broader engineering team. Internal Responsibilities: Attend regular internal practice community meetings. Collaborate with your itD practice team on ind

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff/Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition! Implementing core Xpath, Ypath and Array design during project execution and work with project teams integrating the Core schematics into the full chip schematics, validating design performance and functionalities by running block and chip level simulations using standard industry simulators! Implementing analog and mixed signal circuit design (charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, LDO, thermometers, page buffers, PDNs, level shifters, IO buffers, RTL, Verilog) to meet specifications, validating design performance and functionalities by running block and chip level simulations using standard industry simulators Serve as a technical authority across analog/core teams , solving sophisticated technical problems at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability Develop and productize agentic enablement for circuit design , including AI/LLM-assisted flows that support: environment setup and self-healing configuration, guided simulation and debug, intelligent corner planning and coverage closure, automated schematic/layout checks and review assistance, documentation synthesis and knowledge retrieval from internal sources,<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Design DFT team at Micron, building testability into the heart of advanced memory products. Our work spans circuit innovation, architecture, and methodology, and directly impacts quality, scalability, and manufacturability across Micron’s global portfolio. We collaborate deeply across design, verification, and manufacturing to solve hard problems early and push memory technology forward! As a Design Engineer on the Design DFT team, you play a critical role in ensuring Micron’s memory products are testable, robust, and production-ready. This role blends hands-on circuit design with architectural thinking and forward-looking methodology development. You will influence designs early, partner across disciplines, and help introduce AI-enabled approaches that shape the future of DFT. Responsibilities: Define and implement DFT, testmode, and related design methodology requirements for current and future memory products Design and evaluate new DFT circuit and architectural solutions to improve coverage, scalability, and robustness Influence early design planning by shaping DFT architecture, testability strategies, and reusable design intent Validate DFT solutions through modeling, simulation, and review of circuits, testmodes, and verification results Collaborate across design, verification, product engineering, and manufacturing to meet coverage, cost, and qualit

The Civil Design Lead is responsible for leading the civil design efforts for water infrastructure projects, ensuring designs meet project specifications, industry standards, and regulatory requirements. The role involves coordinating with internal teams and external consultants to deliver integrated, efficient, and cost-effective design solutions. Source: Adani Group | Job ID: 53345

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role We're looking for a Product Design Engineer with deep simulation and structural analysis expertise to help us build hardware that holds up to the demands of daily life. You'll be the analytical backbone of Hark's mechanical engineering team — using FEA and coupled simulation methods to validate design decisions, predict failure modes, and drive structural, thermal, and dynamic performance from the earliest stages of development through production release. This is a hands-on role where simulation directly shapes design: you'll work closely with product design engineers, industrial designers, and reliability teams to ensure that what we build is not just beautiful, but durable, precise, and manufacturable at scale. Responsibilities Lead structural, thermal, and dynamic finite element analysis (FEA) across Hark's hardware portfolio — enclosures, mechanical assemblies, flex systems, and interconnects — from concept through design validation Develop simulation models and methodologies that accurately predict real-world performance under drop, vibration, fatigue, thermal cycling, and mechanical load conditions Translate FEA findings into actionable design recommendations, collaborating directly with product design engineers to iterate geometry,