Design Verification Engineer Intern Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ROLE Lead first-silicon bring-up, characterization, debug, and validation of advanced 3D NAND products. Establish whether silicon meets design intent and datasheet requirements, correlate simulation with measurements, and resolve issues that could affect product qualification, reliability, yield, or SSD/system integration. This role provides a unique opportunity to develop end-to-end expertise across advanced NAND products, spanning circuit design concepts, mixed-signal simulations, first-silicon bring-up, silicon debug, product qualification, and manufacturing readiness. Engineers gain broad exposure to analog, mixed-signal, digital, firmware, memory-array, and system-level behavior while working closely with design, verification, firmware, product, and system teams. RESPONSIBILITIES • Own validation strategies, coverage, and test plans for assigned NAND circuits and functions; define expected behavior, operating corners, and pass/fail criteria from product specifications and design intent. • Lead first-silicon bring-up, characterization, debug, and simulation-to-silicon correlation across voltage, temperature, process, timing, and workload conditions. • Characterize and debug NAND subsystems including reference and bias generation circuits, bandgap references, oscillators, voltage regulators, charge pumps, sensing and page-buffer paths, high-voltage program/er

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Ready to do the most impactful work of your career? At Coinbase , we are uncompromising on our mission to increase economic freedom. The bar is high, the environment is intense, and we like it that way. This isn't a place for complacency, it’s a place to be pushed past your perceived limits. If you're ready to build the future of finance alongside people who refuse to settle for "good enough," you belong here. Coinbase is a remote-first, but not remote-only company. Expect to get together quarterly for intense in-person working sessions called “surges.” learn more about working at Coinbase . Ready to do the most impactful work of your career? At Coinbase , we are uncompromising on our mission to increase economic freedom. The bar is high, the environment is intense, and we like it that way. This isn't a place for complacency, it’s a place to be pushed past your perceived limits. If you're ready to build the future of finance alongside people who refuse to settle for "good enough," you belong here. Coinbase is a remote-first, but not remote-only company. Expect to get together quarterly for intense in-person working sessions called “surges.” learn more about working at Coinbase . Agent Verification builds systems that help Coinbase safely ship software in an AI-native development environment. The team develops automated code review, risk and policy evaluation, CI evidence, and merge controls that reduce routine manual work while preserving human judgment for higher-risk changes. As a Senior Software Engineer, you will design and build reliable backend services and integrations across source control, CI/CD, policy systems, and developer workflows. You will lead the adoption of a consistent and observable merge path, partner with Security, Compliance, Infrastructure, and product engineering teams, and improve how software changes are reviewed and shipped across Coinbase. We are looking for an experienced backend or platform engineer who has built distribute

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root caus

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development. Define and review module interfaces and system-level architecture. Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate RTL design optimization and design‑space exploration Assist in testbench generation and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom methodology for memory design Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis. Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments. Collaborate closely with architecture, design, verification, and physical design / layout teams. Oversee and manage the layout process including floor-planning, placement, and routing. Perform block-level and full-chip verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools. Contribute to cross-group communication to work towards standardization and group success Provide technical mentorship and participate in design and methodology reviews. Drive innovation into the future memory generations and design methodology within a dynamic w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations). Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data Support design rule checking (DRC) of both base and mask layers and interface with physical verification team. Define algorithms for generation of mask data from drawn base layer data. Involve projects across multi-disciplinary teams focusing on layout and mask generation issues About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of hig

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

Test & Evaluation Hardware Design Engineer (Experienced & Senior) Company: The Boeing Company The Boeing Test and Evaluation (BT&E) organization is seeking Hardware Design Engineers to be based in Long Beach, CA , supporting the development and sustainment of our avionics lab and related test activities. You'll have the opportunity to work on groundbreaking projects that will shape the future of the aerospace industry. Our current initiatives include developing an integrated test lab for flight hardware, avionics, and flight simulators. Major programs include AvionX, C-17 and others. As a Hardware Engineer in BT&E, you will play a pivotal role in the design and development of lab hardware and sustainment of new and legacy units. In addition, you will document requirements, develop and maintain test articles and interfaces in support of various programs using the lab. Additionally, you will perform seamless hardware and software integration ensuring all systems work harmoniously together to support qualification and provide support in troubleshooting and resolving lab issues of new and legacy test equipment. Our teams are currently hiring for a broad range of experience levels including Mid-Level or Senior Hardware Design Engineers. Position Responsibilities Include: Own domain-specific hardware architecture, component selection, physical design, and detailed mechanical, electrical, and test engineering Perform systems verification through execution of test procedures Support the development and verification of test methods Develop detailed test procedures, and instrumentation and configuration definition, needed undefined Deve

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary: As an ENGINEER, NAND SILICON DESIGN VALIDATION at Micron, you will be part of an ambitious group committed to developing and validating top-tier NAND Flash memory products. This position is distinct since it covers both pre-silicon concept development and practical post-silicon validation. You will acquire a full understanding of the product lifecycle. You will work on modern technologies, conduct simulations, and compose detailed validation documentation. Your role will be key in identifying and resolving design-related problems to secure outstanding product performance. Your responsibilities will encompass collaborating with R&D teams, designers, and various engineering departments to troubleshoot and validate device testing programs. You will be the key point of contact for critical product-specific issues, ensuring a seamless interface between Research and Development, Manufacturing, Business Units, and Quality Assurance departments. Main Responsibilities: Develop, validate, and qualify new innovative NAND Flash memory products Define and validate product configuration parameters Apply CAD tools and Verilog simulations for build verification and in-depth circuit analysis Identify build marginalities and recom

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. MTS, Interface Pathfinding Hardware Development Engineer About the Role At Micron, our vision is to transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next generation of high-speed interfaces. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Interface Pathfinding Hardware Development Engineer , you will own characterization for a high-speed interface test-chip program: the characterization plan and its success criteria, development of the characterization bench hardware and its automation, the measurement-uncertainty budget, and the correlation report proving the silicon matches the models. You will join a small, senior team spanning analog design, layout, digital design, and verification, working closely with the Chip Lead and the Signal Integrity and Physical Design engineers — driving decisions independently while consulting heavily with other experts across Micron. This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and characterization complexity — including an expanding mandate for AI-enabled engineering leadership across the organization. What You’ll Own Characterization Planning • Derive the electr

We believe that the way people interact with their finances will drastically improve in the next few years. We’re dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid’s network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Seattle, Washington D.C., Raleigh, London, and Amsterdam. Client Engineering is the technical arm of Plaid’s European GTM team. We own our customers’ technical outcomes: designing the right solution, getting it built and live, and keeping it healthy as they grow. We work with the most technically forward companies in European financial services – fintechs, lenders, and payments and wealth platforms – helping them build on payment initiation, account data, verification, and underwriting across UK Open Banking and PSD2. As a Sales Engineer for Plaid Europe, you’ll be a technical lead across the region’s sales team, partnering with 5–6 Account Executives from the first technical conversation through proof of concept to signature. You’ll run technical discovery, design solutions, and demo and prove Plaid’s products to engineers and commercial buyers, making sure every customer’s architectural decisions set them up for long-term success on the platform. You’ll also help build the Sales Engineering function in Europe, from the demo environments, sample apps, discovery frameworks, and integration playbooks the team sells with, to feeding what you hear from customers back into Plaid’s roadmap. Responsibilities Serve as technical lead on active o