Design Verification Engineer Intern Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

We are now looking for Chip Design Internships for the Switch Silicon group. As a Chip Design Intern at NVIDIA's Networking business unit, you'll join a group of passionate engineers to implement the next generation state of the art Switch Silicon chips. In this intern position, you'll be part of a dynamic, technology-focused company while closely engaged with developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Understand the fullchip working flow and build infrastructure for better automation, efficiency. Work in a combined design and verification team and develops test facilities for quality assurance. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: Pursuing BS / MS in electrical / computer engineering and related. A team player with quick learning, good communication and interpersonal skills. Fluent English (both written and spoken). Experience in RTL design or RTL verification is a plus. Strong scripting

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Craft and analyze digital and analog circuits used in the development of memory products including simulating, optimizing, and floor planning DRAM circuits. Collaborate with various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively craft HBM products that optimize all manufacturing functions and assure the best performance, power, cost, quality, reliability, time-to-market, and customer happiness. Innovate and integrate end-toend groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). Employer will accept a Master’s degree in Electrical Engineering, Physics, Computer Engineering, Semiconductor Engineering or a related field and 10 years of experience in the job offered or in a related field. Position requires: 1. High-speed memory design on data paths, from I/O interface to core array 2. 2. Power domain network analysis 3. Memory test architectures like MBIST and production silicon validation 4. Digital design methodologies experience including RTL design, synthesis, and physical implementation 5. ASIC design development using digital design 6. Memory core timing, latency control, and signal integrity consideration in advanced designs <p style="

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. SUMMARY: At Micron , we are transforming how the world uses information to enrich life for all. As a Layout Design Engineering Intern, you will contribute to the development and verification of selected IP layout cells used in memory products. Working alongside experienced layout engineers, you will gain hands-on experience with industry-standard layout methodologies and participate in key activities such as floorplanning, placement, routing, and physical verification. You will also have the opportunity to develop automation solutions that improve engineering productivity, design quality, and efficiency through scripting and AI-supported development. Responsibilities: Develop the layout of selected analog and digital IP layout cells under the guidance of experienced layout engineers. Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification and document findings. Create and deliver technical reports summarizing design work, verification results, and key lessons learned. Design and implement a SKILL-based automation solution to improve layout design or verification processes, increasing engineering efficiency and quality. Support engineering activities through AI-assisted development methodologies and productivity tools. Minimum Qualifications: Student pursuing a Bachelor's degree in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a rela

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff Engineer in Micron’s HBM Product Engineering Component Validation team, you will be an individual contributor responsible for the validation of advanced High Bandwidth Memory (HBM) products. You will use proven knowledge in dynamic random-access memory and high-bandwidth memory architecture to compose validation coverage, implement and analyze validation runs, lead product debug and failure analysis toward a zero-escape validation goal across test modes and product achievements. You will also adopt AI-enabled ways of working, using enterprise AI tools to accelerate your engineering tasks and improve efficiency, work within Micron’s global validation organization and collaborate with groups at different locations. Responsibilities: Translate DRAM/HBM develop intent and architecture into effective verification scope and test cases. Contribute to validation of new and high-risk product features, working with Design Validation, and Systems Engineering. Review design specifications, schematics, and datasheets, provide design feedback and represent the Product Engineering perspective in Design and Verification reviews. Read, analyze, and debug circuit blueprints to detect design-related failure mechanisms, and recommend approaches for verification and fault diagnosis. Perform root-cause analysis and examination of electrical failures (debug) of validation findings, distinguishing developed marginality from process and test-related issues. Apply automation and modern tooling (including

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles and Responsibilities · Plan and execute verification of analog and mixed-signal circuits at block, subsystem, and full-chip levels. · Develop and maintain full-chip mixed-signal simulation environments in which analog circuitry, digital logic, and firmware coexist. · Create schematic and behavioral models for selected blocks to make full-chip simulations feasible, efficient, and sufficiently accurate for the intended verification objective. · Develop verification plans from design data sheets, new feature requests, requirements, interface definitions, and identified risk areas. · Run static and dynamic simulations to identify leakage paths, power-sequencing issues, and unintended circuit interactions. · Perform device-level electrical rule checks, including SOA, snapback, SFB, and related reliability checks. · Perform SPF extraction analysis and fanout, connectivity, and coupling checks. · Execute power-cycling simulations, including power-loss and brownout events. · Run chip-level user-mode simulations that correlate analog subsystems, logic behavior, and firmware algorithms. · Debug complex AMS failures with a system-level outlook, identify root causes, and work with design, firmware, and verification partners to drive closure. · Develop scripts and reusable automation for regression setup, simulation execution, log processing, waveform analysis, result comparison,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles and Responsibilities · Plan and execute verification of analog and mixed-signal circuits at block, subsystem, and full-chip levels. · Develop and maintain full-chip mixed-signal simulation environments in which analog circuitry, digital logic, and firmware coexist. · Create schematic and behavioral models for selected blocks to make full-chip simulations feasible, efficient, and sufficiently accurate for the intended verification objective. · Develop verification plans from design data sheets, new feature requests, requirements, interface definitions, and identified risk areas. · Run static and dynamic simulations to identify leakage paths, power-sequencing issues, and unintended circuit interactions. · Perform device-level electrical rule checks, including SOA, snapback, SFB, and related reliability checks. · Perform SPF extraction analysis and fanout, connectivity, and coupling checks. · Execute power-cycling simulations, including power-loss and brownout events. · Run chip-level user-mode simulations that correlate analog subsystems, logic behavior, and firmware algorithms. · Debug complex AMS failures with a system-level outlook, identify root causes, and work with design, firmware, and verification partners to drive closure. · Develop scripts and reusable automation for regression setup, simulation execution, log processing, waveform analysis, result comparison,

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Anthropic runs some of the largest AI training and inference workloads in the world, across multiple hardware platforms. We work from the chip level up with our silicon partners, and we are now deepening that investment by building a custom silicon team. You will be one of a small number of people covering a large surface. We are opening searches across the key domains below, and we are interested in candidates whose center of gravity sits in any of them: Front-end design Pre-silicon verification Physical design Design for test Analog and mixed-signal Technology and foundry CAD and design infrastructure Packaging, signal integrity, and power integrity This is a role for someone who has shipped silicon, has a realistic relationship with schedules, and is comfortable making consequential calls without a large organization behind them. Key responsibilities Take part in end to end activities for the program: strategy, specification, execution and the technical bar. Write the specifications and interface definitions that others design against and keep them coherent as the architecture converges Make and own directional calls: technology and IP selection, where we build versus buy versus license, and where we take design authority versus rely on partners Build and share AI-assisted approaches to the code-like parts of your domain, and help the team learn what Claude can genuinely accelerate Contribute to the architecture and micro-architecture discussion from your domain's perspective, including the tradeoffs your area imposes on the rest of the chip Partner with Anthropic's inference, performance, kernels, and infrastr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview Our Munich engineering team develops mixed‑signal and IO solutions for next‑generation memory technologies. The group partners closely with global analog, digital, and product teams throughout the design and silicon lifecycle. Role Overview We are hiring an IO Design Architect to design new architecture, analysis, and validation of high‑speed memory IO. This role combines hands‑on circuit understanding with system‑level thinking and close collaboration across multiple design teams. Responsibilities Define and own the IO and PHY concepts for high‑speed memory interfaces Perform block‑level simulation, analysis, and feasibility checks Review and guide schematic‑level implementation to align with architectural intent Support verification, silicon bring ‑up, and debug activities Collaborate with

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

Zoox is on an ambitious journey to develop a full-stack autonomous mobility solution for cities and safely deploy such a robotaxi solution. The System Design and Mission Assurance (SDMA) team plays a foundational role in the company's success, responsible for constructing the safety case and fail-operational design for our autonomous driving robots before public road deployment. We are seeking a highly motivated V&V software development engineer in test (SDET) to join this systems-engineering department. As a V&V SDET, you will be a technical lead, owning the end-to-end validation strategy for critical safety systems while architecting and implementing the advanced software infrastructure required to verify them. This role is coding-intensive, focused on building solutions for high-fidelity testing, scalable automation frameworks, and sophisticated data analysis tools to ensure successful compliance to requirements and mission success. Some examples of tools this role supports: Framework for event definition, orchestration, and verification High-performance C++ and Python-based emulators for vehicle sensors (e.g., Radar, Lidar, and Inertial Measurement Units) to enable realistic, real-time fault injection Robust communication bridges between simulation environments and physical vehicle hardware Automating test management and reporting within lifecycle management tools, e.g. Polarion, JAMA, DOORS. In this role, you will: Lead the design and maintenance of large-scale event-driven software/hardware -in-the-loop (SIL/HIL) testing frameworks, utilizing advanced software patterns to improve modularity and reduce code duplication. Architect and manage end-to-end continuous integration (CI) pipelines to automate the execution of regression suites. Lead root cause analysis for complex system-level failures, developing log mining scripts and visualization dashboards (e.g., Grafana, SQL-based notebooks) to triage failures and track performance metr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets. Own front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions. Develop, maintain, and optimize design constraints (SDC), including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies to achieve optimal PPA. Collaborate closely with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges, improve design robustness, and ensure successful product execution. Analyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements to meet performance, power, area, and schedule objectives. Chip in to the development and enhancement of design methodologies, automation frameworks, and RTL-to-GDS implementation flows, improving engineering productivity, design quality, and time-to-market. Apply strong expertise in CMOS digital and mixed-signal concepts, Verilog/System Verilog, and industry-standard EDA tools to develop scalable and reliable silicon sol

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential! Position Overview As a Principal Design Engineer in NVEG, you will architect, design and sign off the high-speed IO interface of next-generation NAND flash, moving data between the NAND die and the host controller at multi-GT/s rates under tight power, area and signal-integrity limits. You will own IO blocks end to end, from spec and architecture through circuit design, layout guidance, verification and silicon correlation. You will set IO architecture direction across products, lead task forces, and make the key trade-offs that hit aggressive data-rate and power targets. AI is a central pillar of how this team works: you will use AI tools daily and reshape wor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Design DFT team at Micron, building testability into the heart of advanced memory products. Our work spans circuit innovation, architecture, and methodology, and directly impacts quality, scalability, and manufacturability across Micron’s global portfolio. We collaborate deeply across design, verification, and manufacturing to solve hard problems early and push memory technology forward! As a Design Engineer on the Design DFT team, you play a critical role in ensuring Micron’s memory products are testable, robust, and production-ready. This role blends hands-on circuit design with architectural thinking and forward-looking methodology development. You will influence designs early, partner across disciplines, and help introduce AI-enabled approaches that shape the future of DFT. Responsibilities: Define and implement DFT, testmode, and related design methodology requirements for current and future memory products Design and evaluate new DFT circuit and architectural solutions to improve coverage, scalability, and robustness Influence early design planning by shaping DFT architecture, testability strategies, and reusable design intent Validate DFT solutions through modeling, simulation, and review of circuits, testmodes, and verification results Collaborate across design, verification, product engineering, and manufacturing to meet coverage, cost, and qualit

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role Mach Industries is seeking a Ground Systems Mechanical Engineer to design, develop, and deploy ground systems that enable the safe, reliable, and efficient transportation, handling, storage, launch, and operation of next-generation defense platforms. In this hands-on role, you will design, and iterate on ground support equipment (GSE), launch and deployment systems, electro-mechanical interfaces, and supporting infrastructure while optimizing for manufacturability, reliability, safety, cost, and performance. You will work alongside multidisciplinary engineering, manufacturing, test, and operations teams to develop requirements then perform design, analysis, and testing cycles leading to prototype and flight hardware. You will own the engineering deliverables (CAD models, drafting, analytic and test verification) but contribute throughout the entire hardware development lifecycle. This role is ideal for an engineer who enjoys solving practical mechanical challenges, working directly with hardware, and rapidly developing robust systems that enable real-world operations. Key Responsibilities Own the mechanical design and development of ground systems, including ground support equipment (GSE), launch and deployment systems, tran