Design Verification Engineer Intern Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities · Lead pre-silicon readiness activities across new DRAM products, including risk assessment, DFMEA preparation, validation planning, and readiness reviews with cross-functional engineering teams. · Partner closely with Design, Verification, Component Validation, Product Engineering, Product Architecture, System Compatibility Group, and Silicon Strategy teams to identify product risks, define validation coverage, and align debug priorities. · Apply strong technical judgment to analyze circuit behavior, silicon data, validation results, failure signatures, and product-level interactions across design, test, and manufacturing flows. · Drive structured investigation and resolution of silicon findings, including root-cause analysis, experiment planning, evidence review, and alignment of mitigation or screen strategies to project milestones. · Influence product readiness decisions by connecting design intent, silicon behavior, validation results, manufacturing constraints, and customer quality expectations. · Mentor engineers, strengthen technical practices, and help capture lessons learned that improve execution, product robustness, and organizational readiness across future DRAM programs. ·Apply AI-enabled ways of working to improve engineering productivity, including use of approved AI tools for technical research, data synthesis, debug plan

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What’s Encouraged Daily: AI-First Engineering: Deploy AI tools (LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines) as default practice. Continuously identify automation opportunities and rearchitect workflows—specs, simulations, reviews, hand-offs—to be AI-consumable. Build prompt libraries, agents, and scripts that eliminate recurring manual patterns! AI Leadership: Champion AI adoption by evaluating emerging tools, running pilots, and publishing standard methodologies that measurably reduce cycle time or prove quality! Technical Ownership: Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) to meet performance specs, using AI to accelerate exploration, sizing, and verification. Multi-functional Collaboration: Work with integration, design, and Apps teams to define interfaces and evaluate new specifications. Use AI to summarize discussions, reconcile specs, and quantify trade-offs. Mentorship: Document AI-augmented methodologies and teach engineers to work in an AI-first environment—not just which tools to use, but how to rethink engineering with AI. Minimum Qualifications: BS/MS in Electrical Engineering with 8+ years IC design experience Hands-on AI tool usage (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with concrete examples of productivity or design impact Experience redesig

About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Working within the Logical Design team, the Silicon Logical Design Engineer is responsible for a wide range of logical design tasks which require working closely with other engineers within the Silicon department. This person is responsible for helping the team deliver high quality micro-architecture specifications and RTL for Graphcore chips, and assisting the rest of the Silicon teams to ensure we can meet the company objectives for silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practices Essential skills: Degree in Computer Science, Engineering or a related subject Digital design experience in a relevant industry Be highly motivated, a self-starter, and a team player Ability to work across teams and findi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design and implement physical layouts for advanced digital, analog, and mixed-signal circuits used in the development of memory products. Responsible for translating schematics into high quality, manufacturable layouts that meet process rules, performance targets, and schedule commitments, while collaborating closely with cross functional engineering teams. Create physical layouts of transistors, resistors, capacitors, and interconnect structures for digital, analog, and mixed-signal circuits. Perform block-level floor planning, including layout area estimation and optimization. Develop IC top-level floorplans and provide accurate total die area estimates. Execute routing, power bus design, and creation of robust PDN (Power Domain Network) solutions to ensure optimal electrical performance, reliability, and scalability. Ensure layouts comply with foundry process design rules and verify layout-versus-schematic (LVS) and design rule checks (DRC). Apply recommended layout, verification techniques, tools, and design flows to deliver high-quality designs on schedule. Work closely with analog/mixed-signal and digital design engineers to ensure proper layout implementation, including critical matching and symmetry requirements. Collaborate with Design Engineering, Product Engineering, Process Integration, Probe, and Assembly teams to proactively optimize designs for manufacturability, cost, quality, reliability, and time-to-market. Create and maintain layout-related documentation and actively participate in layout and design reviews. Support continuous improvement of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal ASIC Design Engineer About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer , you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant. What You’ll Own Digital Block Architecture & RTL Design Own the micro-architecture and RTL implement

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD intern at NVIDIA, you'll learn and work on the tasks from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. What you'll be doing: Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan Synthesis, RTL/netlist quality check, formal verification, function eco creation Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue Develop and improve entire timing closure flow from frontend (pre-layou

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job responsibilities: · Create SoC Verification plan and develop C/SV/UVM based SoC verification tests · Develop understanding on SoC Architecture and Test controller Architecture · Develop SV / UVM based testcases for Test controller verification, MBIST verification and Functional vectors generation · Develop SV/UVM monitors to measure performance and improve Verification Environment · Interact with Architecture/Design/Tester teams to identify ASIC test vectors and functional patterns requirement · Develop flows to automate verification environment development and drive team · Involve in Vectors Bring-up activity and support ATE/Tester teams for Functional Characterization Job Qualifications · Bachelors/Masters in Engineering. · Minimum 7&#43; years of SOC/IP Verification based on SV/UVM. Proficient in using AI tools and Methodologies · Good understanding on Test controller / MBIST / DFT architecture · Knowledge of industry standard interfaces, such as PCIE, LPDDR*, ONFI/NAND is desired. · Proven experience in ATE/Functional CHAZ vector enablement in Silicon / Wafers and debug abilities on vectors <p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, our vision is to transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, Micron develops technologies that accelerate the transformation of information into intelligence. The DRAM Engineering Group (DEG) creates advanced memory solutions that enable modern applications, including artificial intelligence, high-performance computing, and immersive user experiences. Our team fosters innovation, collaboration, integrity, and continuous learning while solving some of the industry’s most complex engineering challenges. The Semiconductor Design Engineer will contribute to the design, simulation, optimization, and validation of digital and analog CMOS circuits for advanced DRAM and emerging memory technologies. This role provides opportunities to work across the full product lifecycle, from early technology development through product qualification, while collaborating with global design, verification, and manufacturing teams. The successful candidate will develop technical expertise in memory design, circuit analysis, and design automation while supporting the delivery of high-quality products. Responsibilities Design, simulate, analyze, and optimize CMOS memory circuits and functional blocks, including memory arrays, control logic, datapaths, address decoding, and input/output interfaces. Support physical design activities such as floor planning, placement, routing optimization, layout verification, and manufacturability improvements.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing! What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines. Architect features to help silicon debug and support post-silicon validation activities. What we need to see: Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science. 8&#43; years of meaningful work experience. Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digita

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role Mach Industries is seeking a Senior Ground Systems Mechanical Engineer to design, develop, and deploy ground systems that enable the safe, reliable, and efficient transportation, handling, storage, launch, and operation of next-generation defense platforms. In this hands-on role, you will design, and iterate on ground support equipment (GSE), launch and deployment systems, electro-mechanical interfaces, and supporting infrastructure while optimizing for manufacturability, reliability, safety, cost, and performance. You will work alongside multidisciplinary engineering, manufacturing, test, and operations teams to develop requirements then perform design, analysis, and testing cycles leading to prototype and flight hardware. You will own the engineering deliverables (CAD models, drafting, analytic and test verification) but contribute throughout the entire hardware development lifecycle. This role is ideal for an engineer who enjoys solving practical mechanical challenges, working directly with hardware, and rapidly developing robust systems that enable real-world operations. Key Responsibilities Own the mechanical design and development of ground systems, including ground support equipment (GSE), launch and deployment systems, transport fixtures

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Seeking a Principal Engineer – ASIC SoC Design to drive IP, Subsystem, and SoC development for next‑generation memory and storage products, requiring strong hands‑on expertise in micro‑architecture, RTL design, and end‑to‑end SoC execution, along with close collaboration across global teams. Key Responsibilities Own end‑to‑end IP and SOC development from micro‑architecture through RTL compose, integration, and physical hardware assistance. Own IP and Subsystem design from scratch, ensuring high‑quality, reusable RTL. Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis. Define and review module interfaces and system‑level architecture. Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams. Support post‑silicon debug and bring‑up activities. Provide technical mentorship and participate in design and methodology reviews. This role is expected to utilize Micron-approved AI tools and AI-enabled workflows to improve engineering productivity, design quality, automation, and decision-making across the SoC development lifecycle. The engineer will apply AI-assisted solutions for design analysis, documentation, coding, debug, and workflow optimization while ensuring compliance with Micron AI governance standards. Required Qualifications 12&#43; years of hands‑on IP & SoC RTL design experience. Strong expertise in micro‑architecture, Verilog/System Verilog, and RTL integration. Solid kn

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities include, but are not limited to · Responsible for the architecture, design, implementation, and validation of analog and mixed-signal circuits used in NAND Flash across the complete design lifecycle. · Design and develop circuits such as charge pumps, amplifiers, voltage regulators, data converters (ADC/DAC), bandgap references, sensor interfaces, and power-management blocks. · Translate system-level requirements into detailed circuit specifications, architectures, schematics, verification plans, and clear design documentation. · Perform transistor-level design and optimization to meet performance, power, area, noise, and reliability targets. · Conduct DC, AC, transient, noise, Monte Carlo, and corner simulations to verify functionality and robustness across process, voltage, and temperature variations. · Validate block- and chip-level design performance using standard industry simulators, including evaluation of parasitic effects and integration quality. · Participate in cross-functional evaluation of key NAND features and collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, and other partner teams. · Analyze design and silicon issues, drive root-cause analysis, and implement robust corrective actions. · Coordinate technical activities for a small team when required, including design reviews, execution tracking, and knowledge sharing. · Deve