Dft Lead Jobs

What We’re Looking For: We’re looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems. Ideal Background: Experience leading DFT efforts for multiple advanced node SoC tapeouts Nice to Have: Experience leading DFT efforts for large die area (eg reticle-max) chips Experience leading DFT efforts for multi-die/multi-chiplet/MCM designs Experience leading DFT efforts for AI accelerator SoCs

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Lead DFT Engineer Job Description: Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Description : Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Lo

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding opportunity to join a world-class team and make a significant impact in the semiconductor industry! What You'll Be Doing: Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms. Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST, memory BIST, and scan compression. Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology. Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre-silicon through production deployment. Develop and standardize methodologies, processes, and workflows for silicon bring-up, crafting reusable checklists and playbooks. Improve cross-team communication, work, and handoffs. Guide and mentor junior engineers, helping them navigate complex build trade-offs to achieve world-class quality and efficiency. What We Need To See: BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains. Demonstrated knowledge and expertise in defining

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role Summary In this role, you will lead the mechanical design of next-generation outdoor and Camera-Like devices. You will work on products exposed to extreme climates, long-term UV/heat aging, and waterproofing constraints—all while balancing aesthetics, reliability, and manufacturability. Your decisions directly shape products that ship globally and define UI’s leadership in the outdoor category. Responsibilities Drive mechanical architecture and enclosure development specifically for outdoor IP-rated devices, rugged housings, and battery-integrated systems. Validate product performance under extreme outdoor conditions (thermal cycling, UV exposure, waterproofing, vibration, salt spray). Lead DFM/DFT reviews with tooling and manufacturing partners, ensuring high-volume readiness and stable mass production. Collaborate with EE/RF teams t

itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration. Location: Hybrid in Carlsbad, CA or Allentown, PA , or U.S. Remote . Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST). Duration: 14 months We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities: Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging. Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs. Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures. Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability. Collaborate with physic

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Comp

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As part of Tenstorrent’s Automotive Robotics team, you will help design and deliver the core hardware modules inside our next generation chiplet based SoCs for automotive products. You will be the bridge between silicon design, DFT, OSAT partners, and customers to ensure our multi die SiP platforms meet aggressive performance, quality, and safety targets. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced with industry standard ATPG and DFx insertion CAD tools. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Able to translate system and safety requireme

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Job title Senior DFT Engineer Job description We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. Your responsibilities Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include: Building entire chip-level DFT strategies Inserting DFTs, including scan chains, memory BIST, and JTAG Collaborating with RTL, physical design, and verification teams for testabil

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. </li

Job Details: Job Description: About the Group Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Intel Foundry will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IP's. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. Come join us and do something wonderful. The Aerospace, Defense, Government (ADG) - The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, DFT/DFM insertion, ATPG validation methodology and flows. The successful candidate will: </p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive cross-functional collaboration across Design, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor junior engi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. Th

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Build, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor engineers

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Location: Richardson, TX We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Design, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities · Lead the design and execution of sophisticated memory subsystems and top-level integration activities. · Own design planning, technical decision-making, risk assessment, and schedule execution. · Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. · Review design specifications, microarchitecture documents, and implementation plans. · Drive memory array design, including address decoders and data path, internal power supplies, and custom circuit design activities depending o