Dft Lead Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Building, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities Lead the design and execution of complex memory subsystems and top-level integration activities. Own design planning, technical decision-making, risk assessment, and schedule execution. Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. Review design specifications, microarchitecture documents, and implementation plans. Drive RTL, mixed-signal, memory controller, PHY, or custom circuit design activities depending on project needs. Lead design reviews and drive issue resolution across organizations. Mentor early-career engineers and provide technical leadership to project teams. Define and improve develop methodologies applying AI-enabled tools, automation, and standard processes. Support silicon bring-up, debug, characterization, and yield improvement activities. Communicate project status, risks, and mitigation plans to management and collaborators. Required Qualifications BS/MS/PhD in Electrical Engineering, Computer Engineering,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and fin

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in the world—spanning 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs powering Autonomous Machines, Robotics, and Industrial systems. You will innovate at scale, designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that consistently delivers breakthrough performance across multiple high-impact tape-outs each year. What you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms. Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions. Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio. Guide and mentor junior engineers, helping them navigate complex design

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role Great hardware balances performance, manufacturability and serviceability. Mach is building unmanned defense systems at a rate the traditional defense industrial base was never designed for. That takes designs that are built to be built: fast, right the first time, at the lowest cost, and easy to maintain in the field. This is a hands-on technical leadership role with direct reports. As Lead Manufacturing Engineer, Avionics, you'll be Mach's go-to expert on designing electronics, harnesses and avionics boxes so they can be built, tested, installed and maintained quickly and without errors. You'll write Mach's Avionics DFMA guide. You'll push the field forward through research and development (R&D) on new materials, hardware and processes. Key Responsibilities Own the Avionics DFMA guide Write, publish and maintain Mach's Avionics DFMA guide. It should cover: design rules, with the reasoning and test data behind them preferred components, connectors, wire and processes standard features and tolerances worked examples and review checklists Write design-for-manufacturing, assembly and test rules (DFM, DFA, DFT) for PCBAs, wire harnesses, connectors and avionics enclosures (box build). Set connector retention and mate-assurance standards: two-st

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the ID1 fabrication site Process Integration and Yield Enhancement through test development, DOE data analysi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the ID1 fabrication site Process Integration and Yield Enhancement through test development, DOE data analysi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Engineer – HBM Design for Test (DFT) is an experienced technical contributor responsible for the definition, implementation, integration, and support of DFT solutions across HBM core die and base die for current and next‑generation HBM products. This role focuses on driving defined DFT architectures , contributing to DFT specifications, and partnering with multi‑functional teams to ensure DFT features meet test, quality, and manufacturability requirements. The Engineer works closely with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to support successful tape‑out, silicon bring‑up, and qualification. Key Responsibilities Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture and guidelines Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines Ensure DFT implementations support high‑quality, efficient, and manufacturable HBM products Use AI Supported tools and flows where necessary to improve job efficiency Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to: Translate manufacturing and test requirements into actionable DFT implementations. Support alignment between DFT specifications and verification coverage. Identify, debug, and resolve DFT‑related issues during build execution, tape‑out, and silicon bring‑up Serve as a DFT contributor or sub‑d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. The Senior Engineer – HBM Design for Test (DFT) is an experienced technical contributor responsible for the definition, implementation, integration, and support of DFT solutions across HBM core die and base die for current and next‑generation HBM products. This role focuses on driving defined DFT architectures , contributing to DFT specifications, and partnering with multi‑functional teams to ensure DFT features meet test, quality, and manufacturability requirements. The Senior Engineer works closely with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to support successful tape‑out, silicon bring‑up, and qualification. Key Responsibilities Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture and guidelines Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines Ensure DFT implementations support high‑quality, efficient, and manufacturable HBM products Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to: T

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the fabrication sites and Process Integration through test development to increase effective process feedba

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA Silicon Codesign Group is seeking a versatile engineer to join the HW bring-up methodology team. The SCG team is uniquely positioned to have an end-to-end view of the product development cycle - from early architecture definition, through bringup, to product release. What will you be doing: Led end-to-end planning and on-time execution of Nvidia's new chip bringup effort, from pre-silicon through production deployment. Coordinate multi-functional teams across Architecture, Build, Validation, DFT, SW, System, and Operations to drive shared bringup achievements. Improve cross-team communication, work, and handoffs. Develop and standardize methodologies, processes, and workflows for silicon bringup, creating reusable checklists and playbooks. Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules. Lead post-action reviews and convert learnings into concrete process improvements for future silicon and solution bringups. Contribute to post-silicon learnings that feed back into architecture, design, and pre-silicon

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is hiring an ATE Test Development Engineer who can build sophisticated, scalable test solutions on the Advantest V93000 platform using SmartTest 8, custom code, and low‑level tester APIs. This role is ideal for someone who enjoys writing clean, modular software that directly touches hardware, understands how measurements are supposed to work, and can drive experiments that isolate variables across silicon, instrumentation, and test methodology. You will own the development, debug, datalogging, and optimization of ATE test content for NPI and production, ensuring our devices are thoroughly characterized, efficiently tested, and ready for high‑volume manufacturing. This role is hybrid, b ased out of Austin,TX; Santa Clara,CA; or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 10+ years of experience in ATE test development, semiconductor test engineering, or post-silicon validation. You are proficient with Advantest V93000, SmartTest 8, tester APIs, C++ or Java, and Python automation. You understand ATE instrumentation, including DPS, PMU, RF/HSIO, timing sets, multisite execution, and tester-to-DUT

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is hiring a System-Level Test (SLT) Engineer to ensure our silicon behaves predictably when running real workloads in real systems. You’ll build the software and system infrastructure that enables validation tests to operate reliably in manufacturing, while applying structured debug to separate hardware issues from software, interface, and environmental effects. This role is ideal for someone who understands how tests are constructed and how silicon responds under stress—and who can turn that insight into scalable, production-ready solutions. Candidates will be assessed for the appropriate level during the interview process, and the offer level may differ from the level listed in this posting. This role is hybrid, based out of Austin,TX; Santa Clara,CA; or Fort Collins, CO . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 10+ years of experience in system-level test, embedded systems, software architecture, or hardware/software integration, with strong skills in C/C++, Python, or similar languages. You apply object-oriented design principles to build modular, maintainable, and extensible test frameworks

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs