Dft Lead Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Design DFT team at Micron, building testability into the heart of advanced memory products. Our work spans circuit innovation, architecture, and methodology, and directly impacts quality, scalability, and manufacturability across Micron’s global portfolio. We collaborate deeply across design, verification, and manufacturing to solve hard problems early and push memory technology forward! As a Design Engineer on the Design DFT team, you play a critical role in ensuring Micron’s memory products are testable, robust, and production-ready. This role blends hands-on circuit design with architectural thinking and forward-looking methodology development. You will influence designs early, partner across disciplines, and help introduce AI-enabled approaches that shape the future of DFT. Responsibilities: Define and implement DFT, testmode, and related design methodology requirements for current and future memory products Design and evaluate new DFT circuit and architectural solutions to improve coverage, scalability, and robustness Influence early design planning by shaping DFT architecture, testability strategies, and reusable design intent Validate DFT solutions through modeling, simulation, and review of circuits, testmodes, and verification results Collaborate across design, verification, product engineering, and manufacturing to meet coverage, cost, and qualit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DFT (Design for Test) Product Development Engineer in the DRAM Technology group, you will be part of a forward-thinking team of engineers that solves complex problems to develop industry-leading DRAM. In this role, you will gain an in-depth understanding of semiconductor memory functionality and become an expert in the test manufacturing code and testing techniques used to develop, implement, validate, and ensure device performance. You will engage with new technology at the build start to cultivate DFT and Micron’s component test flow philosophy on modern architectures. This will be accomplished through innovation and by multi-functional engagement with partner groups – Build, Test, Technology Development, Manufacturing, Marketing, and Quality Assurance departments. Agentice AI. Responsibilities Partner with Test Manufacturing, Product Engineering, and Design Engineering to provide test guidance, set priorities, and drive improvements in product quality and yield. Develop new DFT concepts and test architectures to support future enhancements in test coverage, efficiency, and test time reduction. Debug and identify root causes of failures using data analysis, elec

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s HIG HBM Digital Design Group is seeking a Digital Design Engineer to contribute to the architecture, RTL development, verification, and delivery of high‑performance digital logic blocks for advanced HBM memory products. In this role, you will translate specifications into robust Verilog/SystemVerilog RTL, evaluate design tradeoffs across power, performance, and area, and apply strong fundamentals in digital logic, computer architecture, and low‑power methodologies. You will collaborate closely with verification, physical design, DFT, CAD, and system architecture teams to deliver high‑quality well‑documented digital designs. Success in this role requires strong technical communication skills, a proactive approach, and the ability to excel in a fast‑paced, highly collaborative engineering environment. Responsibilities: Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post‑silicon debug. Develop high‑quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications. Define and refine micro‑architecture for digital logic blocks, including FSMs, datapath, FIFOs, pipelines, and arbitration logic. Analyze tradeoffs across area, power, latency, and throughput, providing clear documentation and communication of design decisions. Perform CDC/RDC analysis, apply sound clocking and reset strategies, and ide

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer – Design for Test (DFT) in the NVEG organization at Micron Semiconductor Italia, you will be responsible for the integration, optimization, and validation of DFT architectures for advanced NAND Flash memory products. In this role, you will work closely with multi-functional teams to improve testability, product quality, cost efficiency, and time‑to‑market, bringing to bear innovative DFT strategies across digital logic, custom circuits, firmware, and silicon validation. Responsibilities include, but not limited to: • Define, implement, and optimize DFT architectures and test strategies for NAND designs, covering both digital and custom circuit blocks. • Analyze testability and coverage, ensuring compliance with quality, reliability, and manufacturability requirements. • Develop and validate test sequences, NAND test algorithms, and verification methodologies at block and chip level. • Collaborate with multi-functional teams and Product Engineering to support DFT integration, silicon bring-up, debug, and production ramp. • Document DFT architectures, methodologies, and results, contributing to continuous improvement of test quality and efficiency. Min Qualifications • M.S. or Ph.D. in Electrical Engineering, Electronics, or a related field. • Strong understanding of digital design, verification, and test/DFT principles. • Proficiency in programming languages such as C/C++ and Python. • Hands-on experience with simulation and validation methodologies f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Develop, debug, and maintain code that enables the parallel testing of advanced memory devices. Support R&D, interacting closely with global teams, as well as taking part in the designing and debugging of test hardware. Develop efficient and innovative solutions of production test flows through test algo optimization. Design test plans for new tests and test algorithms for DRAM, which cover test software and hardware requirements, defect coverage, characterization, trending, process flow, and test times. Develop test programs for products using primarily C++ coding and Python on Automated Test Equipment (ATE) in the given area followed by test program release to manufacturing areas. Drive innovation and improvement through optimizing test programs by applying more efficient testing methods to reduce product test times and manufacturing costs. Demonstrate a thorough understanding of the device/part as it applies to device/part testing. Automate test processes by writing software to improve work efficiency. Develop tools to help provide better analysis and insight of the terabytes of probe data. Develop new Design for Test (DFT), Design For Manufacturability (DFM), and Design For Reliability (DFR) capabilities. Independently debug and identify root causes of test issues and provide solutions across internal/external groups. Provide meaningful statistical data analysis, analytics and justification of program validation and its release to ensure program quality and data integrity. Evaluate and verify yields/quality with global teams to ensure shipping

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Focus on technology node development to advance next-generation DRAM technologies. Contribute to DRAM product design to enable effective transfer of node development innovations into production products. Collaborate with product engineering and process technology teams to validate designs and help guide technology direction. Perform circuit design and floor planning, including power delivery network (PDN) design. Conduct simulation, debugging, and root cause analysis of design and process issues. Identify failures and provide corrective feedback to block design owners. Deliver design insights and recommendations to Technology Development process teams. Validating device and schematic functionality using memory testing systems. Requirements: Employer will accept a Master’s degree in Electrical Engineering, Computer Engineering, or related field and 2 years of work experience in job offered or in a related occupation. Position requires: 1. CMOS Circuit Design; 2. Digital Logic; 3. Mixed Signal Design; 4. Sense Amplifier; 5. Clock or Data Path; 6. AOCV; 7. Power, IR Drop, or PDN; 8. DFT; 9. Spice or Spectre; 10. Verilog; 11. Parasitic Extraction or SPEF; 12. Floor planning or Routing; 13. Cadence Virtuoso; 14. Python; and 15. Data Analysis (JMP). As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and profes

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Seeking a Principal Engineer – ASIC SoC Design to drive IP, Subsystem, and SoC development for next‑generation memory and storage products, requiring strong hands‑on expertise in micro‑architecture, RTL design, and end‑to‑end SoC execution, along with close collaboration across global teams. Key Responsibilities Own end‑to‑end IP and SOC development from micro‑architecture through RTL compose, integration, and physical hardware assistance. Own IP and Subsystem design from scratch, ensuring high‑quality, reusable RTL. Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis. Define and review module interfaces and system‑level architecture. Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams. Support post‑silicon debug and bring‑up activities. Provide technical mentorship and participate in design and methodology reviews. This role is expected to utilize Micron-approved AI tools and AI-enabled workflows to improve engineering productivity, design quality, automation, and decision-making across the SoC development lifecycle. The engineer will apply AI-assisted solutions for design analysis, documentation, coding, debug, and workflow optimization while ensuring compliance with Micron AI governance standards. Required Qualifications 12+ years of hands‑on IP & SoC RTL design experience. Strong expertise in micro‑architecture, Verilog/System Verilog, and RTL integration. Solid kn

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design/Senior Design Engineer – Auto Place & Route / Digital Implementation (NVE Engineering) Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Introduction The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital, and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with multi-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. Position Overview As a Digital Implementation / Auto Place & Route Engineer in the NVEG organization at Micron Semiconductor Italia, you will drive the physical implementation of advanced NAND Flash digital designs from synthesized netlist through tape-out. In this role, you will own block- and subsystem-level implementation, including floorplanning, power planning, placement, clock tree synthesis, routing, optimization, and physical sign-off. You will partner with RTL, verification, DFT, analog, custom layout, CAD, and product teams to achieve performance, power, area, reliability, and schedule targets. Responsibilities Responsibilities include, but are not limited to: • Own end-to-end RTL-to-GDSII physical implementation for complex digital blocks and subsystems using automated

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Leveraging AI for design quality

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Post-Silicon Yield & RMA Leadership Lead end-to-end investigation of silicon yield loss, field returns, customer escalations, and reliability failures. Drive root-cause analysis for complex silicon issues spanning process, design, test, package, and system interactions. Develop hypothesis-driven debug strategies and coordinate multi-functional execution. Own resolution of critical yield and quality issues through containment, corrective actions, and prevention plans. Device Technology & Process Interaction Analysis Analyze device-level failure mechanisms and process sensitivities impacting ASIC functionality and yield. Evaluate design-process interactions affecting analog, mixed-signal, memory, high-speed I/O, and PCIe PHY performance. Partner with foundry teams to understand process variations, excursions, reliability risks, and technology limitations. Translate silicon learning into actionable design and process improvements. Advanced ASIC Design Interaction & Silicon Debug Lead root-cause investigations involving design-process interactions affecting SRAM, PCIe PHY, ONFI interfaces, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems. Analyze silicon failures across transistor, circuit, block, die, package, and system levels. Drive post-silicon debug activities involving design teams, DFT, product engineering, quality,