Dram Disability Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Introduction The Central Process Integration Engineering (cPIE) Loop Integration team drives process optimization, defect reduction, structural performance improvement, and technology integration across Micron's advanced DRAM and HBM manufacturing network. We are ready for the future! The team serves as the technical owner of critical process loops including FEOL, MOL, CAP, BEOL, Uniformity, and Backside Engineering, partnering closely with Process Engineering, Yield Engineering, RDA, Manufacturing, and Technology Development teams to accelerate yield learning and qualification readiness! Position Overview As a Senior Process Integration Engineer, you will own process loop performance across one or more critical semiconductor manufacturing modules. You will identify process interactions, drive yield improvement, characterize failure mechanisms, and enable successful deployment of new technologies from development through high-volume manufacturing. This role provides opportunities to influence process architecture, conversion strategies, inline monitoring systems, and technology ramp execution while collaborating with global engineering teams across multiple sites. In support of Micron's AI transformation, you will be expected to harness Artificial Intelligence tools and advanced analytics to improve engineering productivity, accelerate problem solving, and enhance process understanding. Responsibilities Drive process loop performance and structural optimization for assigned

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs to ensure functional correctness, performance, power efficiency, and product quality. Develop comprehensive verification plans from architecture and functional specifications in collaboration with architecture and design teams. Create, enhance, and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures. Define and execute coverage-driven verification strategies to achieve functional, assertion, and code coverage goals. Lead debug and root-cause analysis of complex design issues, drive bug resolution, and ensure verification closure. Apply advanced digital and mixed-signal verification methodologies using industry-standard simulation and verification tools. Drive continuous improvements in verification methodologies, automation, regression efficiency, and AI-assisted verification workflows. Collaborate closely with global design, architecture, product engineering, and system engineering teams to ensure successful project execution. Lead verification efforts for major HBM development programs and mentor engineers through technical leadership and knowledge sharing. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. 10+ years of experience in digital and/or mixed-signal design verification with a proven record of deli

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products. Responsibilities Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets. Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities. Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality. Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios. Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market. Minimum Qualifications Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Analog Verification Engineer at Micron Technology, Inc., you will help shape advanced analog verification methodologies for next-generation DRAM products. In this role, you will develop scalable verification solutions, improve coverage and efficiency, and contribute to high-quality silicon through innovation, automation , and close collaboration with design teams. Experience with reliability verification methodologies is a strong plus, but not a requirement; candidates with solid analog verification expertise and a willingness to grow in reliability-focused verification are encouraged to apply. Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path, you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity. Responsibilities Define and drive DRAM analog verifi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the Technology Development — Advanced Modeling & AI Solutions (AMAIS) organization, you will be part of a multidisciplinary team developing next-generation Digital Twins, predictive modeling solutions, and AI-driven technologies that accelerate advanced memory development and manufacturing excellence. You will create predictive digital representations of semiconductor processes, materials, structures, equipment, and products across DRAM, NAND, and advanced packaging technologies including HBM. Leveraging physics-based modeling, computational methods, machine learning, GenAI, large language models (LLMs), and agentic AI frameworks, you will enable technology co-optimization, design-space exploration, process optimization, yield improvement, and accelerated technology learning. Working at the intersection of engineering fundamentals, manufacturing data, and digital engineering, you will develop scalable predictive and prescriptive solutions that connect process, structure, performance, yield, reliability, and cost. This role offers the opportunity to influence critical technology decisions, drive fab-technology co-optimization , and advance Micron's leadership in data-driven semiconductor memory innovation. Qualifications: Independence – be comfortable executing activities and needs Experience in algorithm development, numerical methods, and scientific computing Solid experience with Plasma, FPM, HAR etching, and MC modeling Experience with Wet Pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has transformed innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are redefining how the world uses information to enrich life. We are looking for Layout Build engineer at our Micron Technology’s DRAM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Responsibilities: Build and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for timely delivery of block-level layouts with acceptable quality. Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Optimally copresentingith Global engineering teams to assure the success of layout project. Minimum Qualification: Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Execution & PI Ownership Lead day‑to‑day Process Integration execution for assigned DRAM modules within the Advanced Technology & Engineering (ATE) organization. Own yield ramp, stability, and integration readiness for assigned scope during technology transfer, pilot, and early HVM phases. Drive root cause investigations for top yield detractors using DOE, SPC/FDC, FMEA, 8D, and structured problem‑solving methodologies. Ensure process window margin, manufacturability, and reliability requirements are met and sustained. Champion adoption of Best‑Known Methods (BKM) and site‑to‑site learning to reduce variability and accelerate learning cycles. Technology Transfer & Ramp Support Execute DRAM technology transfer activities from TD or donor fabs to ID1 under guidance from M2/M3 leadership. Support new product introduction (NPI), process qualification, and customer ramp readiness. Coordinate inter‑fab learning reviews, gap assessments, and corrective action follow‑through. Support extended international assignments (3&#43; months) for training and technology transfer as required. People Leadership & Coaching Manage and develop a team of Process Integration engineers (NCG and experienced). Provide technical guidance, mentoring, and coaching on PI fundamentals, module ownership, and execution rigor. Set clear priorities, expectations, and deliverables aligned with ramp milestones and fab n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will contribute to the design and delivery of next‑generation memory products by working across circuit design, layout, and validation. You will apply simulation, modeling, and verification skills to improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments. This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs. Responsibilities: Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling. Build reusable, a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Department Overview: DRAM Engineering (DRAM Memory) focuses on designing and developing Micron’s industry leading dynamic random access memory products. The team drives process R&D, product design, and technology development for cutting edge DRAM nodes, including DDR5, LPDDR, HBM, and GDDR products that form the foundation of Micron’s global revenue leadership. We work across architecture, engineering, and business teams to evaluate innovative memory solutions and influence product direction. If you’re excited about solving complex challenges in DDR and emerging memory technologies, you’ll find strong impact and collaboration here! We are seeking an experienced Distinguished Member of Technical Staff (DMTS) Design Engineer to join the DRAM System team. This role is at the center of memory innovation. You will analyze current and next-generation memory technologies, identify performance and design gaps, and guide teams on future memory direction. Your work will directly influence architecture, product strategy, and competitive positioning, making it both highly visible and technically rewarding. This position is intended to be part of the Technical Leadership Program at Micron. This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Location: Boise, ID or San Jose, CA Responsibilities:

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information into intelligence through industry-leading memory and storage solutions. The Process Development Engineering team drives innovation for future DRAM and HBM technologies by developing and optimizing semiconductor manufacturing processes that enable next-generation memory products. Our engineers work at the intersection of advanced research and high-volume manufacturing to solve complex technical challenges and accelerate technology advancement. As a Process Development Engineering Intern, you will gain hands-on experience in semiconductor process development while working on a dedicated technical project within a fast-paced research and development environment. Under the mentorship of experienced engineers, you will collaborate across process and equipment teams to develop innovative solutions that meet demanding product requirements. The internship concludes with a formal presentation of your project results to technical and leadership audiences. Responsibilities Develop and optimize semiconductor processes that meet physical and electrical performance requirements for current and future memory products. Partner with multi-functional process and equipment engineering teams to identify and implement process improvements. Perform root-cause analysis and failure-mode analysis to identify process limitations and develop corrective actions. Conduct fundamental research to support next-generation memory technologies and process innov

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is a global leader in memory and storage solutions, driving innovation in next-generation DRAM technologies that power artificial intelligence, cloud computing, and advanced computing applications. The Dry Etch Process Development team develops and optimizes advanced plasma etch processes that enable future memory scaling and support groundbreaking semiconductor manufacturing. As a Dry Etch Process Development Engineering Intern, you will gain hands-on experience developing and optimizing semiconductor etch processes in a collaborative research and development environment. Working under the mentorship of experienced engineers, you will contribute to a technical project focused on process development, experimentation, data analysis, and technology innovation. The internship provides broad exposure to semiconductor processing and culminates in a presentation of project results to engineering and leadership teams. Responsibilities Research and develop innovative solutions that support future memory technologies and advanced dry etch process development. Develop, complete, and analyze experiments to optimize dry etch processes and improve product performance. Perform statistical analysis of technology development and pilot manufacturing data to identify trends and drive process improvements. Collaborate with process, equipment, integration, and multi-functional engineering teams to solve complex technical challenges. Apply AI-Enabled analytical tools, Leveraging AI, programming, or automa